R. McConnell. Massively parallel SIMD computing on a single chip. In Proc. of the 11th Symposium on HighPerformance Chips at Stanford University. 1999. Home/Search Document Not in Database Summary Related Articles Check |
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A System for Evaluating Performance and Cost of SIMD.. - Herbordt, Cravy, Sam, .. (1999) (Correct)
....been one of the major technological diculties. Even current designs have largely solved this problem, however: a board level instruction issue rate of 100MHz was achieved in 1995 by Bolotski s Abacus [3] and systems with a chip level issue rate of 200MHz are commercially available from PixelFusion [28]. The likely applications continue to be graphics [28, 36] and vision [4, 10, 24, 21] although compression [41] neural nets [23] chess (the IBM Deep Blue coprocessors) and scienti c computing [32] are some of the other possibilities. Corresponding to the increased capabilities of single chip ....
.... designs have largely solved this problem, however: a board level instruction issue rate of 100MHz was achieved in 1995 by Bolotski s Abacus [3] and systems with a chip level issue rate of 200MHz are commercially available from PixelFusion [28] The likely applications continue to be graphics [28, 36] and vision [4, 10, 24, 21] although compression [41] neural nets [23] chess (the IBM Deep Blue coprocessors) and scienti c computing [32] are some of the other possibilities. Corresponding to the increased capabilities of single chip (or single substrate) SIMD arrays is an increase in design ....
McConnell, R. Massively parallel simd computing on a single chip. In Proc. of the 11th HOT Chips Symposium (1999).
Visibility Driven Rasterization - Meißner, Bartz, Günther, Straßer (2001) (Correct)
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R. McConnell. Massively parallel SIMD computing on a single chip. In Proc. of the 11th Symposium on HighPerformance Chips at Stanford University. 1999.
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