J. Cong and Y.-Y. Hwang, "Structural gate decomposition for depthoptimal technology mapping in LUT-based FPGA design," in Proc. 33rd ACM/IEEE Design Automation Conf., 1996, pp. 726--729.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....lut based fpga Performance oriented technology mapping is usually performed in 3 steps as shown in figure 1 : a) decomposition : the network is decomposed into a set of 2 input lut. It has been shown that decomposition increases the solution space for covering, thus leading to better solutions [5]. This is the reason for the 2 lut decomposition step. Lots of decomposition methods have been proposed for the pre processing. Dmig [1] a polynomial algorithm, provides equivalently good results as compared to other methods [5] b) covering : it is then covered by a network of K lut. ....

....the solution space for covering, thus leading to better solutions [5] This is the reason for the 2 lut decomposition step. Lots of decomposition methods have been proposed for the pre processing. Dmig [1] a polynomial algorithm, provides equivalently good results as compared to other methods [5]. b) covering : it is then covered by a network of K lut. Researchers have mainly focused on static delays optimization, since dynamic delays optimization is a NP Hard problem. Delay of a node depends exclusively on the delay of nodes on paths from the pi to this node. Current algorithms make ....

J. Cong and Y.-Y. Hwang. Structural gate decomposition for depth-optimal technology mapping in lut-based fpga designs. In Proc. ACM/IEEE Design Automation Conf., Las Vegas, NV, June 1996.

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J. Cong and Y.-Y. Hwang, "Structural gate decomposition for depthoptimal technology mapping in LUT-based FPGA design," in Proc. 33rd ACM/IEEE Design Automation Conf., 1996, pp. 726--729.

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CONG,J.AND HWANG,Y. 1996. Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA. In Proceedings of the Design Automation Conf. 726--729.

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J. Cong and Y. Huang, "Structural gate decomposition for depth-optimal technology in LUT-based FPGA designs," ACM Trans. Design Automation Electron. Syst., vol. 5, no. 2, pp. 193--225, 2000.

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J. Cong and Y. Huang, "Structural gate decomposition for depth-optimal technology in LUT-based FPGA designs," ACM Trans. Design Automation Electron. Syst., vol. 5, no. 2, pp. 193--225, 2000.

....LUT delay model. It is applicable to any bounded Boolean network. Given a general Boolean network as input, if it is not bounded , we first transform it into a two input simple gate network by using any of the decomposition algorithms, such as tech decomp in SIS [17] DMIG [3] and DOGMA [12]. The optimality of our algorithm holds not only for two input simple gate networks, but for any bounded general Boolean network as well. The HeteroMap algorithm has two phases. In the first phase (Section III A) according to the topological order from PI to PO, HeteroMap uses the dynamic ....

J. Cong and Y.-Y. Hwang, "Structural gate decomposition for depth-optimal technology mapping in LUT-based FPGA design," in 33rd ACM/IEEE Design Automation Conf., June 1996, pp. 726--729.

....is not available. During the technology mapping stage, we are able to perform depth optimal mapping, but the solution space is greatly confined because we are committed to a fixed circuit structure as the starting point for mapping. Since the delay optimal decomposition for mapping is NP hard [1], it is unclear how far away we are from the optimal solution when logic decomposition and technology mapping are performed simultaneously. The goal of this research is to combine logic decomposition and technology mapping for LUTbased FPGA designs, with delay minimization as the primary ....

....for area minimization is NP hard [8] A more extensive survey of LUT based technology mapping is available in [9] Previous studies on simultaneous decomposition and mapping went back to Chortle d, which guarantees depth optimal technology mapping for simple gate tree networks. Afterwards, dogma [1] studied structural gate decomposition for depth optimal technology mapping of general networks. Although the problem of delayoptimal structural decomposition is NP hard, the work shows that Permission to make digital or hard copies of all or part of this work for personal or classroom use is ....

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J. Cong and Y.-Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design," 33rd ACM/IEEE Design Automation Conference, 1996, pp. 726-729.

....of depth less than 3. However, if the decomposition shown in Figure 1(c) is carried out for node v, a mapping solution of depth equal to 2 can be obtained. Even for K bounded networks, the depth of mapping solutions computed by FlowMap may decrease if gates are further decomposed before mapping [4]. Several gate decomposition routines have been used for LUT mapping. The tech decomp and the speed up in SIS [10] and the dmig in [1] focus on minimizing the number of levels in the decomposed network. They do not directly minimize the depth of the mapping solution. Chortle d [6] computes ....

....N K into a 2 input network N 2 such that for any other 2 input network decomposition N 2 of N, MMD (N 2 ) MMD (N 2 ) There are two issues related to the problem of gate decomposition. 1) A smaller depth might be obtained when several gates are decomposed simultaneously instead of independently [4]. This is because the intermediate nodes could be shared during the decomposition of multiple gates of the same functional type. 2) Gate decomposition can be performed before the mapping phase in a two step approach or embedded into the mapping process being part of an integrated approach. For ....

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Cong, J. and Y.-Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA," in UCLA Computer Science Dept. Tech. Report CSD-950045, (December 1995).

....simultaneously minimize both S(v) and R(v) to compute optimal FRT mapping solutions. 3 As in [19] 1] 2] we assume that the initial circuit is K bounded. When a circuit is not K bounded, we can use gate decomposition algorithms, such as balanced tree decomposition [20] DMIG [21] or DOGMA [22], to decompose those gates with more than K fanins beforehand. Before proceeding to present our algorithm, we first introduce the definition of K cuts which is widely used in this paper and some other FPGA mapping algorithms [19] 2] 1] In a directed graph with one sink and one source, a cut ....

J. Cong and Y.-Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUTbased FPGA Desings," ACM Transactions on Design Automation of Electronic Systems, vol. 5, no. 2, 2000, http://www.acm.org/todaes/V5N2/L266/paper.ps.gz.

....E i c of node c shown in Figure 2(a) with control number i from 0 to 3, respectively. Pan and Liu [22] showed that to examine all K LUTs for a node v, it sufficed to examine all the K LUTs that can be 2 When a circuit is not K bounded, we can use gate decomposition algorithms in [2] 3] [8] to decompose gates with more than K fanins. 4 c 0 a 0 b 1 i 1 0 c 1 i 2 1 a 1 b 2 c 0 a 0 b 1 i 1 0 c 1 i 2 1 c 0 a 0 b 1 c 0 (b) c) d) e) i 2 a b c i 1 (a) Fig. 2. Expanded circuits. derived from the K cuts in E Kn v . With the assumption that the weight of ....

J. Cong and Y.-Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. In 33rd ACM/IEEE Design Automation Conference, pages 726--729, 1996.

....Section 3 addresses the NPcompleteness of the problems. Section 4 presents two new algorithms, named DOGMA and DOGMAm, for structural gate decomposition. Experimental results are presented in Section 5 and Section 6 concludes the paper. A preliminary version of this work was published in DAC 96 [CoHw96] without the proofs of theorems and considered only single gate decompositions. 2. Problem Formulation 2.1. Definitions and Preliminaries A combinational Boolean network N can be represented by a directed acyclic graph N = V,E) where each node v V represents a logic gate and each directed ....

Cong, J. and Y.-Y. Hwang, "Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Designs," Proc. ACM/IEEE 33rd Design Automation Conf., pp. 726-729, 1996.

....LUT circuit with the MDR ratio of no more than OE. As in [CoDi94, CoWu96, PaLi96b] this paper assumes that the initial circuits are K bounded. When a circuit is not K bounded, we can use gate decomposition algorithms, such as balanced tree decomposition [BrRS87] DMIG [ChCD92] or DOGMA [CoHw96], to decompose the gates with more than K fanins. To solve Problem 1, our algorithm, named TurboSYN, works in three steps: 1) label computation (to be explained later) with sequential functional decomposition to search for a mapping solution with the minimum MDR ratio, 2) mapping generation and ....

J. Cong and Y.-Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. In 33rd ACM/IEEE Design Automation Conference, pages 726--729, 1996.

....exists a functionally equivalent LUT circuit with the MDR ratio of no more than OE. As in [6, 11, 19] this paper assumes that the initial circuits are K bounded. When a circuit is not K bounded, we can use gate decomposition algorithms, such as balanced tree decomposition [2] DMIG [4] or DOGMA [9], to decompose the gates with more than K fanins. To solve Problem 1, our algorithm, named TurboSYN, works in three steps: 1) label computation (to be explained later) with sequential functional decomposition to search for a mapping solution with the minimum MDR ratio, 2) mapping generation and ....

J. Cong and Y.-Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUTbased FPGA Design. In 33rd ACM/IEEE Design Automation Conference, pages 726--729, 1996.

....not known [Men97] 5. EXPERIMENTAL RESULTS We demonstrate the effectiveness and quality of the developed IP protection approach on the problem of technology mapping for the set of MCNC benchmark and six industrial strength designs. For LUT based technology mapping we used the CutMap algorithm [Con96b]. Tables 1 and 2 show the results obtained when the algorithm was applied to an original and corresponding watermarked design from the MCNC benchmark suite and from a set of six available industry strength designs. The first four columns in both tables specify the name of the mapped circuit, the ....

J. Cong and Yean-Yow Hwang. Structural gate decomposition for depthoptimal technology mapping in LUT-based FPGA design. 33rd Design Automation Conference, pp.726-9, 1996.

....networks, i.e. each gate in the network has at most K fanins 3 . In the remaining of this paper, all the circuits are assumed to be K bounded. 3 When a circuit is not K bounded, we can use the gate decomposition algorithm, such as balanced tree decomposition [BrRS87] dmig [ChCD92] or DOGMA [CoHw96], to decompose the gates with more than K fanins. We use G(V; E;W ) to denote the retiming graph of a sequential circuit, where V is the set of nodes which represents gates in the circuit, E is the set of edges which represents the connection between gates, and W is the set of edge weights ....

J. Cong and Y.-Y. Hwang. Structural Gate Decomposition for Depth-Optimal Technology Mapping in LUT-based FPGA Design. In 33rd ACM/IEEE Design Automation Conference, pages 726--729, 1996.

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J. Cong and Yean-Yow Hwang. Structural gate decomposition for depthoptimal technology mapping in LUT-based FPGA design. 33rd Design Automation Conference, pp.726-9, 1996.

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