T. Hanyu, M. Kameyama. A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic. IEEE J.Solid State Circuits, vol. 30, no 11, pp. 1239-1245, Nov. 1995.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....using arithmetic circuits often benefit from using alternatives to binary number systems. For example, residue and redundant number systems can reduce or eliminate the ripple through carries which are involved in normal binary addition or subtraction, resulting in high speed arithmetic operations [3, 4]. In spite of these potential advantages, practicality of multiple valued logic design heavily depends on the availability of circuit realizations which must be competitive with present day binary technologies. The attempts to built integrated circuits employing multi stable state devices and ....

....except 0 have two or more representations by a string of digits. This allows us to make carry dependent on the next two lower digits at most, but no other. Fast multiple valued arithmetic in redundant balanced number system as well as in redundant unbalanced number system have been presented in [3], 29] and [8] 28] correspondently. 3 Multiple valued functions A multiple valued function is a discrete function whose input and output variables take two or more values. Formally, an n variable multiple valued function f#x 1 ; x n # is a mapping f : M M , with the variables x i ....

T. Hanyu, M. Kameyama, A 200 MHz pipelined multiplier using 1.5 V-supply multiple-valued MOS current-mode circuits with dual-rail source-coupled logic, IEEE Journal of Solid-State Circuits, 30, 11, (1995), 1239-1245.

....a given number are available. The most significant digit does not depend on the least significant bit. The carry into a digit is computed only from (at most) the next two lower digits, but no other, enabling fast arithmetic operations. Multiple valued arithmetic in redundant balanced number system [9], 10] as well as in redundant unbalanced number system [11] 12] have been presented. Some other number representations which have potential advantages over binary have been studied, including overlap resolution number system based on signed continuous valued digits, allowing to perform ....

....The frequently used linear sum operation can be performed simply by wiring, resulting in a reduced number of active devices in the circuit. Several prototype chips of current mode CMOS circuits have been fabricated, showing better performance compared to corresponding binary circuits ( 7] [9], 11] 15] 16] It is believed that current mode designs can allow better noise margin than voltage mode CMOS designs. Regrettably, the unique characteristics of CMOS binary logic, namely that of zero static power dissipation in either stable state, similar output impedance in either state ....

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T. Hanyu, M. Kameyama, A 200 MHz pipelined multiplier using 1.5 V-supply multiplevalued MOS current-mode circuits with dual-rail source-coupled logic, IEEE Journal of Solid-State Circuits 30, 11, (1995), 1239-1245.

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T. Hanyu, M. Kameyama. A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic. IEEE J.Solid State Circuits, vol. 30, no 11, pp. 1239-1245, Nov. 1995.

No context found.

T. Hanyu, M. Kameyama. A 200 MHz Pipelined Multiplier Using 1.5 V-Supply Multiple-Valued MOS Current-Mode Circuits with Dual-Rail Source-Coupled Logic. IEEE J.Solid State Circuits, vol. 30, no 11, pp. 1239-1245, Nov. 1995.

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