S. Sidiropoulos and M. Horowitz, "A semidigital dual delaylocked loop", IEEE J. of Solid-State Circuits, pp 1083-1092, Nov. 1997.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....Level of the Hierarchy Rd Energy (pJ) Wr Energy (pJ) D cache 222.8 246.3 I mem (per instr) 51.6 56.8 Row buffer 500.1 2740.6 DRAM bank 3702.2 3286.2 Table 3: Average energy consumption per access. 15 Clocks Other The clocking system includes 1 main PLL and 16 distributed local DLLs [30]. The clock network is laid out in the chip using an H tree structure to minimize skew. To estimate the overall energy of the clocking system, we estimate and add the contributions of several components, namely PLL, DLLs, buffers, and distribution lines. Such contributions are estimated based on ....

S. Sidiropoulos and M. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal on Solid-state Circuits, vol. 32, pp. 1683--1692, November 1997.

....bin smaller than larger and thus averages out for a sufficiently large histogram period. Sampler input offsets will skew the histogram measurements and need to be minimized before this measurement technique is used. Given the ability to position to a clock edge within 1 16 of a FO 4 delay [31] and measure the timing of clock edges to an arbitrary precision [17] it appears possible to constrain phase errors to within about 3 of a FO 4 delay. This is significantly better than previously reported data for multi phase clock generators. Maneatis in [23] reports DNL phase spacing errors of ....

....to layout 1. Recall delay sensitivity, as defined in Chapter 3, is the percent change in delay divided by the percent change in supply voltage and is unitless. 1. Previous application of the adjustable interpolators use a thermometer coded DAC to permit dynamic changes to the current weights [31]. However, for this application, the adjustment codes are only changed during an initial calibration sequence so less complex binary weighting is instead used. The DAC currents do not even have to be monotonic as the calibration algorithm can check all possible adjustment codes and pick the ....

S. Sidiropoulos et. al. "A Semi-digital Dual Delay-Locked Loop," IEEE Journal of Solid State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.

....incoming data. This block is normally a phase or delay locked loop that aligns the on chip clock signal to the incoming data stream. The test chip prototype relies on the peripheral timing loop of a dual loop delay locked loop (DLL) architecture that locks to the synchronously transmitted clock [43]. The components of this loop are described in detail in Section 4.5, and will show that it also does not represent the worst case critical path. Instead, the critical path in the I O subsystem is set by the delay requirements of the clock distribution network which is limited by the minimum cycle ....

....forms. In the case of a source synchronous parallel interface design that transmits a dedicated clock signal along with the data, timing recovery can be achieved with a single delay locked loop. This section first describes a digital implementation of the peripheral loop of a dual loop DLL design [43] that aligns the internal clock signal with the incoming I O clock. A fully digital peripheral loop is possible by again leveraging the delay controlled nature of digital gates with an adaptively regulated supply and replace precision analog circuit elements that would otherwise be used. Even the ....

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S. Sidiropoulos and M. Horowitz, "A semi-digital dual delay-locked loop," IEEE Journal of Solid-State Circuits, Nov. 1997, pp. 1683-1692.

....as discussed in Section 3.2.1. The primary source of static phase offset in this design would be due to up and down current mismatch in the charge pump. Using active feedback to compensate the mismatch can keep the static phase error to less than 1 5 FO 4, as demonstrated by Sidiropoulos in [88]. Figure 4.22: Hogges phase detector for serial data. 7] There are several difficulties in using this phase detector. One is the additional digital processing necessary to determine transitions. The processing delay adds to the delay of the feedback loop and reduces the phase margin of the loop. ....

....with the transistor mismatches. Because transistor mismatches are static (albeit random) offset correction schemes, such as an open loop correction at the start up period of the circuit, can be applied. For example, static phase error can be corrected using programmable interpolators (as done in [88]) that adjust each phase individually. Similarly, input offset voltage can be corrected using techniques commonly applied in ADCs (such as [83] and [101] The challenge is to perform the offset corrections with very little performance overhead for the receivers. Because the samplers are cycled at ....

S. Sidiropoulos, M.A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, Nov. 1997, vol.32, no.11, pp. 1683-92 181

....main limitation of DLL s is their limited phase capture range. A new dual DLL architecture that eliminates this problem, while keeping the clock jitter and offset low is proposed. The implementation of the circuit building blocks and the results from a fabricated prototype are also discussed [20] [21]. The final chapter summarizes the contributions of this work and discusses areas of further development. Chapter 2 Signalling and Clocking Signalling and Clocking This work focuses on circuits and architectures for high performance parallel links. In order to provide a framework for ....

S. Sidiropoulos and M. Horowitz, "A Semi-digital dual Delay Locked Loop", IEEE Journal of Solid-State Circuits, vol. 32, no. 11, pp. 1683-1692, Nov. 1997.

....the 3 bit link timing noise budget of 0.23T symbol,pp corresponds to only 3 of a cycle of the multi phase clocks. Ring oscillators can generate clocks with low timing noise, but work best when locked to stable timing sources. Since the received signal is noisy, a dual loop architecture is used [49] to generate clocks with low jitter and to phase lock to the received signal. The primary loop locks to a stable, low noise reference clock for low jitter, while the second loop aligns the clocks to the input data. 1. The approximate square law mapping of timing to voltage noise (see Equation ....

....generated in a ring oscillator locked to a stable clock source, but the clocks have no phase relationship to the received signal, and could be slightly off in frequency. To lock the clocks to the received signal, a second, delay locked loop (DLL) is added to the primary PLL, as shown in Figure 2. 8 [49]. The primary PLL (upper loop) phase locks a multi stage VCO to a stable reference clock, with high loop bandwidth to minimize random and coupled noise. The secondary DLL (lower loop) generates receiver clocks from the VCO clocks, adjusting their phase to the receive signal, using low bandwidth ....

S. Sidiropoulos, M.A. Horowitz, "A Semidigital Dual Delay-Locked Loop," IEEE Journal of Solid-State Circuits, Nov. 1997, vol.32, no.11, pp. 1683-92

....The phase mixing technique using quadrature clocks provides unlimited phase shift capability. However, phase mixing uses two small slew rate clocks to obtain linear results. Therefore, this approach has the disadvantage of the increased dynamic noise sensitivity and jitter. In the semidigital DLL [4], a digitally controlled phase interpolator uses internally generated 30 spaced clocks through the dual DLL architecture. Although noise sensitivity issues on the phase interpolation could be alleviated by smaller interpolation intervals, inherent digital nature causes dithering around zero phase ....

S. Sidiropoulos and M. A. Horowitz, "A semidigital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683--1692, Nov. 1997.

....only 0.1 mm . The chip is packaged in a 52 pin leaded chip carrier (LDCC) package with internal power planes for controlled impedance. Receiver timing recovery circuits were not implemented in this test chip but can be easily integrated by incorporating a peripheral DLL loop as described in [17]. Fig. 16(a) shows the eye diagram at the output of the transmitter with the equalizer disabled. The swing shown is 100 mV. The peak current drive can be as high as 20 mA. Fig. 16(b) shows the eye diagram after 1 m of 7 mil 0.5 oz GETEK PCB trace. The diagram shows that this medium causes enough ....

S. Sidiropoulos and M. Horowitz, "A semidigital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683--1692, Nov.

....circuitry in high speed interface. The common difficulty with DLLs is the limited phase range which may invoke failure in locking at start up and supply temperature variations[1 3] Dual loop architecture was used to achieve unlimited phase shift by using phase interpolation in 2nd loop[2]. Phase interpolation uses two small slew rate clocks to obtain linear results, which has the possibility of the increased dynamic noise sensitivity and jitter. We introduce a new dual loop DLL architecture, which is shown in Fig. 1. Reference loop is composed of 4 main delay cells and locked to ....

S. Sidiropoulos, et al., "A semidigital dual delay-locked loop," IEEE JSSC, vol.32, pp.1683-1692, Nov.

....Level of the Hierarchy Rd Energy (pJ) Wr Energy (pJ) D cache 222.8 246.3 I mem (per instr) 51.6 56.8 Row buffer 500.1 2740.6 DRAM bank 3702.2 3286.2 Table 3: Average energy consumption per access. Clocks Other The clocking system includes 1 main PLL and 16 distributed local DLLs [29]. The clock network is laid out in the chip using an H tree structure to minimize skew. To estimate the overall energy of the clocking system, we estimate and add the contributions of several components, namely PLL, DLLs, buffers, and distribution lines. Such contributions are estimated based on ....

S. Sidiropoulos and M. Horowitz. A Semidigital Dual Delay-Locked Loop. IEEE Journal on Solid-state Circuits, 32(11):1683--1692, November 1997.

....and occupies 0.3mm 2 . The input signal is 2 oversampled by 8 offset cancelled receive amplifiers per receive clock cycle. The samples are processed by a phase controller to position the receive clocks at the center and the edge of the data eye using a semi digital dual delay locked loop (DLL) [3]. The quiet supply p p jitter of the receive clock is 39ps with 0.33ps mV supply sensitivity. It allows for plesiochronous clocking with a frequency tolerance of 400ppm. The worst case phase resolution is 20ps. Introduction Recent developments in high speed serial links have enabled multi Gb s ....

....reducing the area, power, and noise sensitivity of high speed I O circuits. In this paper, we describe a CDR circuit with the same goals of being amenable to large scale integration while capable of operating in excess of 4Gb s. System Architecture Fig. 1 shows the CDR architecture adapted from [3]. A low power, noise insensitive core DLL generates 8 clock phases. The DLL has an inverter based delay line regulated by a linear regulator as described in [2] The absolute phase positions of the 8 clock phases are simultaneously adjusted by 4 differential timing verniers, each composed of two ....

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S. Sidiropoulos and M. Horowitz, "A semidigital dual delaylocked loop," IEEE J. Solid State Circuits, vol. 32, pp. 16831692, Nov. 1997.

....the value is 81 pJ. Recall that the processor is simple and that its 28 16 bit instructions are optimized for intelligent memory operation [24] The energy consumed by the clock in the whole chip is estimated to be 907 pJ per cycle assuming 1 main PLL [6] and 16 distributed local DLLs [38] with meshed clock signal routing [24] The calculation is performed for 800 MHz and 1.8 V and extended for di erent voltage and frequency as required by schemes described in Chapter 4. The energy required for di erent cache operations is shown in Table 5.4. Table 5.5 is the complete spreadsheet ....

S. Sidiropoulos and M. Horowitz. A semidigital dual delay-locked loop. IEEE Journal of Solid-state Circuits, 32(11):1683-1692, November 1997.

....in the chip. More details to be found in [3, 27] 4. 2 Computing the Energy Consumed To estimate the energy consumed by the chip, we have applied scaling down theory to data on existing devices reported in the literature, and have used several techniques and formulas reported in the literature [2, 10, 15, 17, 26, 30, 44, 45, 51]. The complete set of tables that we have generated can be found in [3] In this paper, we only give an overview of the procedure we followed. To compute the total energy, we add the contributions of the processor cores, clock distribution, memory hierarchies, and miscellaneous. The energy in the ....

....instruction. This energy includes an average of 44 pJ required to fetch the instruction from the I memory. The energy consumed by the clock distribution in the entire baseline chip is estimated to be an average of 907 pJ per cycle. This gure assumes 1 main PLL [2] and 16 distributed local DLLs [45] with meshed clock signal routing [27] To compute the energy consumed in the memory hierarchy, we follow [10, 15, 26] First, we classify memory hierarchy accesses into reads and writes, and based on what level of the hierarchy they reach. In addition, there are displacements of dirty lines from ....

S. Sidiropoulos and M. Horowitz. A semidigital Dual Delay-Locked Loop. IEEE Journal of Solid-state Circuits, 32(11):1683-1692, November 1997.

....will be the size of the largest phase step. For our application, we would like to keep this jitter below 50 ps. An interpolator with a 2 ns range controlled by a 6 bit counter would have 31.25 ps jitter and satisfy our requirements. The phase interpolator topology is based on the design from [22] and shown in Fig. 5.4. The structure is similar to that of the delay elements except that the input differential pairs and current sources are replaced by two sets of unit cells. One set of unit cells has the differential clock signal PHI as input, while the other set has the differential clock ....

S. Sidiropoulos and M. Horowitz. A semi-digital dual delay locked loop. IEEE Journal of Solid-State Circuits, 32(11):1683--1692, Nov 1997.

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S. Sidiropoulos and M. Horowitz, "A semidigital dual delaylocked loop", IEEE J. of Solid-State Circuits, pp 1083-1092, Nov. 1997.

No context found.

S. Sidiropoulos, and M. Horowitz, "A semidigital dual delay-locked loop", IEEE Journal of Solid-State Circuits, Vol. 32, pp. 1683 - 1692, Nov. 1997.

....mode [44] Adaptively adjusting the loop gain depending on the frequency error is possible and has been implemented in [45] E. Clock Recovery DLL The per pin clock recovery DLL by itself has a triple loop architecture, shown in Fig. 21. In addition to the conventional dual loop DLL proposed in [55], the third loop is necessary to generate multiphase clocks for the 1:5 demultiplexing receiver. The first loop generates multiple phases from the reference clock and the second loop selects two among them and interpolates them to generate a tracking phase. The 50 duty Fig. 20. Transient ....

....The interpolator is basically a collection of inverters with their outputs tied together and 2:1 multiplexers that select the signals to their inputs. For a smooth transition of the output edge at all operating frequencies, the bandwidth of the interpolating stage must scale accordingly [55]. Again, the adaptive supply allows the simple CMOS inverters to have this property. Fig. 23. Die micrograph of the prototype chip. TABLE I PROTOTYPE CHIP CHARACTERISTICS V. MEASUREMENT RESULTS The adaptive supply serial link test chip was fabricated in 0.25 m standard CMOS technology. Fig. ....

S. Sidiropoulos and M. Horowitz, "A semidigital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683--1692, Nov. 1997.

....parallel link architecture is presented in Fig. 4. It consists of several parallel data links that run between two chips and has a separate parallel clock line whose delay through the channel matches the data link delays [6] Given this matching, a dual loop delay locked loop (DLL) [11] at the receiver uses the synchronous clock signal to accurately align the on chip clocks to the receivers to sample the incoming data at the most optimal point. One can build the DLL out of static inverters, and use it as the feedback system that determines the correct voltage for running the ....

....DLL architecture that uses the core DLL to generate evenly spaced clock edges that span 360 and drive into a peripheral loop that selects an adjacent pair of edges, and interpolates between them to finely align a clock edge relative to Fig. 12. Digital peripheral loop. the input I O clock [11]. The original implementation of this dual loop architecture uses analog differential delay buffers in the core delay line and interpolator with a sophisticated replica biasing scheme [12] However, the core DLL in this implementation serves a primary role by setting the required voltage of ....

[Article contains additional citation context not shown here]

S. Sidiropoulos and M. Horowitz, "A semi-digital dual delay-locked loop," IEEE J. Solid-State Circuits, vol. 32, pp. 1683--1692, Nov. 1997.

....the normal data transmission begins. The clock recovery DLL is a triple loop architecture. The first loop generates multiple phase clocks from the reference clock, and the second loop selects two phases among them and interpolates them to recover a clock phase with 360 degrees tracking capability [8]. The third loop again generates multiple phase clocks from this recovered clock, which are required by the 1:5 demultiplexing receiver. The serial link test chip was fabricated in a 0.25 m standard CMOS process. The chip micrograph is shown in Figure 5 and performance is summarized in Figure 6. ....

S. Sidiropoulos and M. Horowitz, "A semidigital dual delay-locked loop," IEEE JSSC, Nov. 1997, 1683-1692.

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