C. Piguet, J. Zahnd, "STG-Based Synthesis of Speed-Independent CMOS Cells", Workshop on Exploitation of STG-based Design Technology, St. Petersburg, Russia, July 6-7, 1998  Home/Search Document Details and Download
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Asynchronous negative logic synthesis from STG-like.. - Starodoubtsev (Correct)
....CKCK CKCK CK CK QQ 0 1 1 12 11 10 1 2 3 5 6 4 7 8 Figure 7: State diagrams for reduced STG ACiD WG workshop, St.Petersburg 1998 N.Starodoubtsev. Asynchronous negative logic. 5 5 Pseudometrics 1.3 STG with USC violation 1. 3 STG with USC violation Let us consider the D flip flop from [4] Drawn by our tool it represented in Figure 3. Corresponding state diagram is given in Figure 5a Notice that there are no two equal states in this diagram. Each state is unique. In the other words we can say that the STG in Figure 3 satisfies to unique state coding (USC) condition. Our approach is ....
....one condition or another. A behaviour similar to given in Figure 3 can be represented in another form if USC violation is permitted. Corresponding STG is given in Fugure 4 while corresponding state diagram is given in Fugure 5b. It is the first difference of our approach from one of the paper [4]. 1.4 Concurrency The next difference concerns to concurrent vs. sequential style of description which we use. When comparing two STGs representing two similar behavior we can see that in Fugure 3 a single state corresponds to each places. It is a sequential style of behaviour description. We ....
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C.Peguet, J.Zahnd. STG-Based Synthesis of Speed-Independent CMOS Cells. Workshop on Exploitation of STG-based Design Technology. St.Petersburg, July 6-7, 1998.
Design of Speed-Independent CMOS Cells from Signal Transition.. - Piguet, Zahnd (1998) Self-citation (Piguet Zahnd) (Correct)
....[5] We also assume the property of semimodularity [2, 5] which amounts to say that there are no critical races in the corresponding state graph. The signal transition graph of Figure 2 can be synthetized with the Petrify tool [17] The resulting logical equations correspond to latches [16, 20]. Therefore, the resulting D flip flop structure is the well known master slave or C 2 MOS D flip flop. As shown in [4] such a flip flop is not speed independent due the clock inverter delay. 3. STG based CMOS circuit design 3.1 CMOS gates A realistic model of a CMOS gate [6, 7] is that of ....
C. Piguet, J. Zahnd, "STG-Based Synthesis of Speed-Independent CMOS Cells", Workshop on Exploitation of STG-based Design Technology, St. Petersburg, Russia, July 6-7, 1998
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