C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and veri cation of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769-786, June 1999.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....temporally is not novel. This ordering can be achieved through graph transformations that reduce concurrency similar to the theory developed by Vanbekbergen [13] Timed Petri nets, timed finite state machines, and other bounded delay formalisms have been used to reason about timed circuits in [14] [20] Component databooks include waveforms showing relative signal orderings, and orderings have been applied to micropipeline latches and controllers [21] 23] These methodologies can achieve extremely efficient circuits; indeed, the tag unit in RAPPID, used as the primary example in this ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, "POSET timing and its application to the synthesis and verification of gate-level timed circuits," IEEE Trans. Computer-Aided Design, vol. 18, pp. 769--786, June 1999.

....it is possible to reduce branching in the timed state space by adding fewer relations to the set. Local time semantics and partially ordered sets (POSETs) remove orderings in the zone on sets of independent concurrent signal transitions reducing the representation size of the timed state space [10, 24, 25, 57, 65, 66]. POSET reduction in the timing analysis of Timed Petri nets (TPN) Petri nets with timers on the places yields a significant reduction in the number of zones associated with each marking [66] The algorithm in [66] implements the POSET reduction on concurrent independent signal transitions. ....

....of the reduced state space due to the structural complexity of the model. This research extends the modular synthesis approach in [69] to level ruled Petri nets to further reduce the size of the reachable state space through syntactic abstraction. The partial order in the timing information in [10, 65] is similar to that found in [24, 25] and like the approach in [25] does not require extra reference clocks for synchronization. The basis for the new algorithm is actually presented in [25] and is based solely on the time separation of transitions, but an initial implementation on timed Petri ....

C. J. Myers, T. G. Rokicki, and T. H. Y. Meng, "POSET timing and its application to the synthesis and verification of gate-level timed circuits," IEEE Transactions on Computer-Aided Design, vol. 18, pp. 769--786, June 1999. 213

....of timing assumptions to guarantee conformance of an implementation to its speci cation. 1 Introduction To increase performance, circuit designers are beginning to experiment with timed circuits. Timed circuits are a class of circuits that rely on timing information for correct functionality [1, 2, 3, 4]. This is evidenced by experimental designs such as the Intel RAPPID instruction length decoder in [5] and the IBM guTS microprocessor in [6] Although RAPPID is asynchronous and guTS is synchronous, both designs use formal timing assumptions to achieve better performance. Because these circuits ....

....in the TEL structure. Formally, an allowed trace of a TEL is a failure if any of the following conditions hold [49] 1. A constraint rule on an event is not satis ed when the event res; a ba b [0,0] c] 0,0] c] c] 0,0] c] 0,0] 7,9] 7,9] 7,9] 7,9] c [1,5] c [2,4] [ a b] a b c]d [2,4] a b] b) a) Figure 1: A TEL structure speci cation for a C element (a) and its environment (b) 4 2. A constraint rule on an event expires before the event res; 3. A disabling rule on an enabled place becomes false; 4. There are no enabled transitions (i.e. ....

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C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and verication of gate-level timed circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 18(6):769-786, June 1999.

....allowed by the state space are found in order to create a correct logic implementation [52] If the synthesis algorithm is given an incomplete state space, it cannot be guaranteed to generate logic that correctly responds to all inputs to the circuit. Orbits, presented by Myers and Rokicki in [58, 59, 53], takes a somewhat different approach. It reduces the number of regions per untimed state by using partially ordered sets (or POSETs) of events rather than linear sequences to construct the geometric regions. Instead, the algorithm generates only one geometric region for any set of firing ....

....restriction) In some cases, the single behavioral rule restriction can be worked around through transformations on the initial graphs [50] however the transformations cause a large increase in the complexity of the graphs which need to be analyzed. This thesis extends the algorithms presented in [58, 53] to work with much more flexible specifications. 1.2 Contributions This thesis makes three main contributions to the area of synthesis and verification of timed circuits. The first contribution is in the area of specification. This thesis introduces 9 timed event level(TEL) structures, an ....

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Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. Poset timing and its application to the synthesis and verification of gate-level timed circuit. IEEE Transactions on CAD 18, 4 (June 1999), 769--786.

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C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and veri cation of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769-786, June 1999.

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C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng, \POSET: Timing and Its Application to the Synthesis and Veri cation of GateLevel Timed Circuits", IEEE Transactions on Computer-Aided Design, Vol. 18, No. 6, pp. 769-786, Jun. 1999.

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C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and veri cation of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769-786, June 1999.

....it is possible to reduce branching in the timed state space by adding fewer relations to the set. Local time semantics and partially ordered sets (POSETs) remove orderings in the zone on sets of independent concurrent signal transitions reducing the representation size of the timed state space [20, 21, 22, 23, 24, 25]. POSET reduction in the timing analysis of Timed Petri nets (TPN) Petri nets with timers on the places yields a significant reduction in the number of zones associated with each marking [24] The algorithm in [24] implements the POSET reduction on concurrent independent signal transitions. ....

....states that do not already exist in the allowable runs of the net; thus, the larger equivalence class contains more timed states from the set of reachable states reducing the number of equivalences classes needed to represent the timed state space. This is the essence of the POSet al..gorithm in [22, 23, 24, 25]. This algorithm though has a couple sources of ine# ciency. The first is the need to maintain two separate zones. The second is that operating on place transition firings can substantially increase the number of zones needed to represent the timed state space. This second problem can be ....

C. J. Myers, T. G. Rokicki, and T. H. Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Transactions on Computer-Aided Design of Integrated Circuits, 18(6):769--786, June 1999.

....to LPNs to further reduce the size of the reachable state space through syntactic abstraction. It first presents a new timing analysis algorithm for LPNs that can be applied to systems that are beyond the capacity of existing algorithms. The new algorithm is required because existing algorithms in [22,3] only support a partial order in timing information and not a partial order in the state space exploration. The partial order in the timing information in [22,3] is similar to that found in [4,19] and like the approach in [19] does not require extra reference clocks for synchronization. The basis ....

....be applied to systems that are beyond the capacity of existing algorithms. The new algorithm is required because existing algorithms in [22,3] only support a partial order in timing information and not a partial order in the state space exploration. The partial order in the timing information in [22,3] is similar to that found in [4,19] and like the approach in [19] does not require extra reference clocks for synchronization. The basis for the new algorithm is actually presented in [19] and is based solely on the time separation of transitions, but an initial implementation on timed Petri nets ....

[Article contains additional citation context not shown here]

Myers, C. J., T. G. Rokicki, and T. H. Y. Meng, POSET timing and its application to the synthesis and verification of gate-level timed circuits, IEEE Transactions on Computer-Aided Design 18 (1999), 769--786.

....includes steps to decompose a speci cation into basic events. These events are then translated to simple TEL structures which are composed together in sequence, in parallel, and in con ict as dictated by the structure in the speci cation. The timing analysis algorithms such as the one shown in [65, 9, 10, 55] are applied 3 VHDL AFSM THSE State Graph Logic Equations Gate Netlist Layout TEL Structure Compilation STG Timing Analysis Logic Synthesis Technology Mapping Physical Design Performance Analysis Verification Figure 1.1. Design ow for timed circuit design. to a TEL structure to nd ....

....number of zones can explode in highly concurrent systems. The reason for this explosion in the number of zones is that every possible sequence of concurrent events results in a di erent zone, even though these sequences result in the same untimed state. To solve this problem, a 9 POSet al..gorithm [65, 69] is proposed to consider partial ordered sets of events rather than the linear sequences. This algorithm can reduce the number of zones substantially. Belluomini extended the POSet al..gorithm to TEL structures and applied it to both synchronous and asynchronous designs [7, 6, 9] In [55] Mercer ....

Myers, C. J., Rokicki, T. G., and Meng, T. H.-Y. POSET timing and its application to the synthesis and verication of gate-level timed circuits. IEEE Transactions on Computer-Aided Design 18, 6 (June 1999), 769-786.

....necessary to e#ciently find all reachable timed states. Approaches based on regions or discrete time rapidly explode. Zones can do better, but explode for highly concurrent systems. We developed POSET timing which performs analysis on partially ordered sets of events rather than linear sequences [11, 10, 3, 1]. This eliminates false causality, and it can be orders of magnitude more e#cient. The runtimes for the verification of various sizes of a stari circuit, a self timed FIFO, are shown in Figure 11. It has been shown that a region based tool, timed COSPAN, runs out of 1 GByte of memory for 3 ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769--786, June 1999.

....is necessary to eciently nd all reachable timed states. Approaches based on regions or discrete time rapidly explode. Zones can do better, but explode for highly concurrent systems. We developed POSET timing which performs analysis on partially ordered sets of events rather than linear sequences [11, 10, 3, 1]. This eliminates false causality, and it can be orders of magnitude more ecient. The runtimes for the veri cation of various sizes of a stari circuit, a self timed FIFO, are shown in Figure 11. It has been shown that a region based tool, timed COSPAN, runs out of 1 GByte of memory for 3 stages. ....

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. POSET timing and its application to the synthesis and verication of gate-level timed circuits. IEEE Transactions on Computer-Aided Design, 18(6):769-786, June 1999.

....is a partially ordered set relating various clock values or transition times, it is possible to reduce branching in the time state space by adding fewer relations to the set. Local time semantics or partially ordered sets (POSETs) remove orderings in the zone on sets of independent transitions [7, 8, 21, 22] reducing the representation size of the timed state space. POSET reduction in the timing analysis of Timed Petri nets (TPN) Petri nets with timers on the places yields a significant reduction in the number of zones stored at each state [23] The algorithm implements the POSET reduction on ....

C. J. Myers, T. G. Rokicki, and T. H. Y. Meng. POSET timing and its application to the synthesis and verification of gate-level timed circuits. IEEE Transactions on ComputerAided Design of Integrated Circuits, 18(6):769--786, June 1999.

....Finally, even though the number of interleavings is reduced, in [10] 11] one region is still required for every firing sequence explored to reach a state. If most interleavings need to be explored, these techniques could still result in state explosion. The algorithm presented in [14] 15] [16] significantly reduces the number of regions per untimed state by using partially ordered sets (or POSETs) of events rather than linear sequences to construct the geometric regions. Using this technique, untimed states do not have an associated region for every firing sequence. Instead, the ....

....only one geometric region for any set of firing sequences that differ only in the firing order of concurrent events. This algorithm is shown in [15] to result in very few geometric regions per untimed state. The entire timed state space is explored, so it can be used for both verification [15] [16] and synthesis [17] However, it is limited to specifications where the firing time of an event can only be controlled by a single predecessor event. This is known as the single behavioral place restriction. In [18] we presented an approximate algorithm for exploring the entire state space with ....

[Article contains additional citation context not shown here]

C. J. Myers, T. G. Rokicki, and T. H.-Y. Meng. Poset timing and its application to the synthesis and verification of gate-level timed circuit. IEEE Transactions on CAD, 18(4):769--786, June 1999.

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