Sun Microsystems, SBus Specification B.0, Sun Microsystems, Inc., Mountain View, California, 1990. Home/Search Document Not in Database Summary Related Articles Check |
This paper is cited in the following contexts:
Making Parallel Simulations Go Fast - Reynolds, Jr., Pancerella.. (1992) (1 citation) (Correct)
....processor. The prototype interface between a host, a Sparc 1e, and the 32 bit general purpose auxiliary processor, a 25 MHz Motorola 68020, is a dual ported RAM connecting the Sun SBus and the auxiliary processor. The SBus has a bandwidth of about 100 megabytes per second for 32 bit words [SBus90]. We expect a potential throughput of 25 megabytes per second from host to auxiliary processor. Each AP has 256 Kbytes of RAM expandable up to 1Mbyte to store synchronization programs and related data structures (See [Reyn92] Panc92] and [Srin92] Furthermore, each ....
Sun Microsystems, SBus Specification B.0, Sun Microsystems, Inc., Mountain View, California, 1990.
Reduction Operations in Parallel Discrete Event Simulations - Carmen M. Pancerella (1994) (Correct)
....latency time is approximately two milliseconds. Each auxiliary processor is a 25 MHz Motorola 68020 microprocessor with 256 Kbytes of RAM. The host auxiliary processor interface is implemented with a dual ported RAM, where a Sparc 2 accesses the dual ported RAM through a Sun SBus interface [SBUS90]. The parallel reduction network consists of three ALU s in a binary tree shaped network. The minor cycle time is 150 nanoseconds. The pipelining in the reduction network is performed synchronously. r 97 The prototype hardware limits state vectors to size eight; each of the eight components is ....
Sun Microsystems, SBus Specification B.0, Sun Microsystems, Inc., Mountain View, California, 1990. 172
Design and Performance Analysis of Hardware.. - Reynolds, Jr.. (1993) (4 citations) (Correct)
....processor could be changed to allow for data loss in the same way that the current path from AP to HP operates. The host processor, a Sparc 1e, accesses the dual ported RAM via its HP interface, which is the Sun SBus. The SBus has a bandwidth of about 100 megabytes per second for 32 bit words [SBus90]. We expect a potential throughput of 25 megabytes per second from host to auxiliary processor. 5.3. Parallel Reduction Network The ALU s in the prototype parallel reduction network require 40 nanoseconds to perform a 32 bit fixed point addition; hence, it will take 80 nanoseconds to perform a ....
Sun Microsystems, SBus Specification B.0, Sun Microsystems, Inc., Mountain View, California, 1990.
A Host Interface to the DTM Network - Ahlgren, Pink, Lindgren.. (1992) (1 citation) (Correct)
....to release the connection. ffl DTM Disconnect.indication: Issued by the service provider to indicate that the connection has been released. The service also has primitives for changing the allocated bandwidth. See the service specification for more details [3] 3 SBus characteristics The SBus [8] is a chip level interconnect bus between components such as processors and memory in systems based on microprocessors. It has a maximum clock frequency of 25 MHz, and a 32 or 64 bit data path. Data transfers are supported in sizes of 1, 2, 4, 8, 16, 32 and 64 bytes. The 8 byte and larger ....
Sun Microsystems, Inc., 2550 Garcia Avenue, Mountain View, CA 94043, USA. SBus Specification B.0, Revision A of December 1990. Part number 800-5922-10.
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