Makoto Sugihara, Hiroshi Date, and Hiroto Yasuura. A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem. In Proceedings IEEE International Test Conference (ITC), pages 465--472, Washington, DC, October 1998.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....system level constraints on power consumption. Existing test access mechanisms are ad hoc and do not directly address the problem of minimizing testing time under place androute and power constraints. Related prior work has either been limited to test scheduling for a given test access mechanism [5, 11], or to determining the optimal number of internal scan chains in the cores [1] The latter requires redesign of the scan chains for each customer and thereby affects core reuse. We are interested This research was supported in part by the National Science Foundation under grant number ....

M. Sugihara, H. Date and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. Proc. International Test Conference, pp. 465--472, 1998.

....as a major bottleneck in SOC design [15] A major challenge confronting the system integrator is test scheduling, which determines the order in which the various cores are tested. A combination of built in self test (BIST) and external testing must often be used to achieve high fault coverage [2] [13]. An effective test scheduling approach must minimize testing time while addressing the following issues: 1) resource conflicts between cores arising from the use of shared TAMs and on chip BIST engines; 2) precedence constraints among tests; and 3) power dissipation constraints. Test scheduling ....

....shop scheduling problem [2] We formally define this problem in Section II. Most recent test scheduling techniques for SOCs use heuristics that address only certain aspects of the problem. These include selecting the best test for a core from a set of potential tests supplied by the core vendor [13], approximate vertex cover of a resource constrained test compatibility graph with a view to limit power consumption [5] and reordering of tests to detect defects earlier during manufacturing test [9] The use of test protocols [11] tree growing algorithms for power constrained scheduling [12] ....

M. Sugihara, H. Date, and H. Yasuura, "A novel test methodology for core-based system LSIs and a testing time minimization problem," in Proc. Int. Test Conf., 1998, pp. 465--472.

.... self test (BIST) 3, 4] and techniques for minimizing power during scan testing [5, 6, 7] Power consumption is especially important for SOCs since test scheduling techniques for system integration attempt to reduce testing time by applying scan BIST vectors to several cores simultaneously [8, 9]. Therefore, it is extremely important to decrease power consumption while testing the IP cores in an SOC. Test data volume is another problem faced in SOC test integration. One way to alleviate this problem is to use BIST. However, BIST can only be applied to SOCs if the IP cores in them are ....

M. Sugihara, H. Date and H. Yasuura, "A novel test methodology for core-based system LSIs and a testing time minimization problem", Proc. ITC, pp. 465--472, 1998.

....approach to the SOC test integration problem [4, 3, 15] The next challenge confronting the system integrator is test scheduling, which determines the order in which the various cores are tested. A combination of BIST and external testing must often be used to achieve high fault coverage [2, 14]. An effective test scheduling approach must address the following issues: a) SOC testing time minimization, b) resource conflicts between cores arising from the use of shared TAMs and on chip BIST engines, c) precedence constraints among tests, and (d) power dissipation constraints. 1 This ....

.... SOCs is especially challenging since it is equivalent to the NP hard m processor open shop scheduling problem [2] Most recent techniques use heuristics that address certain aspects of the problem, e.g. selecting the best test for a core from a set of potential tests supplied by the core vendor [14], limiting power dissipation by using a resource constrained test compatibility graph [6] reordering tests to detect defects earlier during manufacturing test [10] the use of test protocols [11, 12] and tree growing algorithms for power constrained scheduling [13] However, all of the above ....

M. Sugihara, H. Date and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. Proc. ITC, pp. 465--472, 1998.

....case, the system integrator may design BIST logic that is shared by multiple cores. In order to minimize the testing time, the test resources in the system (test buses, BIST logic) should be carefully allocated cores, and the tests for the cores should be optimally scheduled. Sugihara et al. [5] recently addressed the problem of selecting a test set for each core from a set of test sets provided by the core vendor and scheduling these tests in order to minimize the testing time. Each test set consists of a subset of patterns for BIST and a subset of patterns for external testing. This ....

....the test sets for any two cores can be assigned identical starting times, and (ii) external testing can be carried out for only one core at a time, i.e. there is only one test access bus at the system level. We formulate a generalized test scheduling problem that includes the problem addressed in [5] as a special case. The main contributions of the paper are summarized below. ffl We relate the general problem of test scheduling to the NPcomplete open shop scheduling problem [2] ffl We relate a special case of the scheduling problem to the problem of open shop scheduling with two ....

[Article contains additional citation context not shown here]

M. Sugihara, H. Date and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. Proc. Int. Test Conf., pp. 465--472, 1998.

....designer to trade off testing time with area overhead by varying tests data widths, the precise relationship between the testing time and the test access architecture has not been formally studied. Related prior work has either been limited to test scheduling for a given test access mechanism [6, 7, 20], or to determine the optimal number of internal scan chains in the cores [1] The latter requires redesign of the scan chains for each customer and thereby affects core reuse. While [1] presents several novel strategies for TAM design (e.g. multiplexing, daisy chaining and distribution) it does ....

M. Sugihara, H. Date and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. Proc. International Test Conference, pp. 465--472, 1998.

....integrator) may design BIST logic that is shared by multiple cores. In order to minimize the testing time, the test resources in the system (test buses, BIST logic) should be carefully allocated to the various cores, and the tests for the cores should be optimally scheduled. Sugihara et al. [16] recently addressed the problem of selecting a test set for each core from a set of test sets provided by the core vendor and scheduling these tests in order to minimize the testing time. If a core is not BIST ed, the core vendor may provide external test sets augmenting various BIST pseudorandom ....

....test length if the core is not BIST ed) and a subset of patterns for external testing. This requires the core vendor to provide multiple test sets for each core, with the test sets containing varying proportions of patterns for BIST and external testing. Test scheduling is formulated in [16] as a combinatorial optimization problem, which is then solved using a heuristic method. The authors make two restrictive assumptions (i) every core has its own BIST logic, i.e. the BIST components of the test sets for any two cores can be assigned identical starting times, and (ii) external ....

[Article contains additional citation context not shown here]

M. Sugihara, H. Date and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. Proc. International Test Conference, pp. 465--472, 1998.

....Scan Chain (q bits) MUX Select (2 bits) SDO p bits Scan Controller Figure 2. Virtual Scan Chain that is p q 2 Bits Long The problem of reducing the test time for cores has been attacked from several different angles in recent literature [Aerts 98] Jas 98] Hamzaoglu 99] Rajski 98] Sugihara 98] Scan chain architectures for corebased designs that maximize bandwidth utilization are presented in [Aerts 98] A technique for compression decompression of scan vectors using cyclical decompressors and run length coding is described in [Jas 98] Both of these techniques apply to cores with ....

....data. Another approach for reducing test time is to use built in self test (BIST) A modular BIST approach that allows sharing of BIST control logic among multiple cores is presented in [Rajski 98] A novel technique for combining BIST and external testing across multiple cores is described in [Sugihara 98] Designing a core with BIST is an alternative to designing a core with a virtual scan chain. However, there are several advantages to developing a core with a virtual scan chain compared with BIST: It is non trivial to achieve high fault coverage with BIST. Inserting test points to improve ....

Sugihara, M., H. Date, and H. Yasuura, "A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem," Proc. of International Test Conference, pp. 465-472, 1998.

....transparent to the system integrator. Core DFHTC Core Test Data Tester Test Data Tester Figure 1. Concept of a DFHTC Core The problem of reducing the test data and test time for cores has been attacked from several different angles in recent literature [Aerts 98] Jas 98] Rajski 98] Sugihara 98] Scan chain architectures for core based designs that maximize bandwidth utilization are presented in [Aerts 98] A technique for compression decompression of scan vectors using cyclical decompressors and run length coding is described in [Jas 98] Since a DFHTC core is fully compatible to an ....

....test vectors a DFHTC core achieves a high fault coverage with a very small number of deterministic test vectors. For these reasons, the system integrator may prefer a DFHTC core to one with BIST. A novel technique for combining BIST and external testing across multiple cores is described in [Sugihara 98] However there are several disadvantages with this technique. It requires multiple test sets for each core with each test set having different components for BIST and external testing. It requires a considerable amount of hardware for scheduling the tests for the different cores. Moreover, since ....

Sugihara, M., H. Date, and H. Yasuura, "A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem," Proc. of International Test Conference, pp. 465-472, 1998.

No context found.

M. Sugihara, H. Date, H. Yasuura, "A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem," Proc. of International Test Conference (ITC), pp.465--472, October 1998.

No context found.

Makoto Sugihara, Hiroshi Date, and Hiroto Yasuura. A Novel Test Methodology for Core-Based System LSIs and a Testing Time Minimization Problem. In Proceedings IEEE International Test Conference (ITC), pages 465--472, Washington, DC, October 1998.

No context found.

M. Sugihara, H. Date, and H. Yasuura, "A Novel Test Methodology for CoreBased System LSIs and a Testing Time Minimization Problem," in Proceedings IEEE International Test Conference (ITC), pp. 465--472, IEEE Computer Society Press, Oct. 1998.

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M. Sugihara, H. Date and H. Yasuura. A novel test methodology for core-based system LSIs and a testing time minimization problem. Proc. Int. Test Conf., pp. 465--472, 1998.

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