P. Briggs. Register allocation via graph coloring. Technical Report CRPC-TR92218, Rice University, Houston, TX, April 1992.  Home/Search   Document Details and Download   Summary   Related Articles   Check

....storage in AR, b) storage in AR followed by MX, and (c) spilling to data memory DM. The last two alternatives require the insertion of extra register transfers. in which the graph coloring procedure is called iteratively [67] Further improvements of these principles have been described [68] [70]. In practice, several of the assumptions made above may not be satisfied. First of all, most practical processors have a heterogeneous register structure. Extensions of the technique have been proposed, to take register classes into account during graph coloring [68] 70] Furthermore, the ....

....been described [68] 70] In practice, several of the assumptions made above may not be satisfied. First of all, most practical processors have a heterogeneous register structure. Extensions of the technique have been proposed, to take register classes into account during graph coloring [68] [70]. Furthermore, the graph coloring approach assumes that the live range of each value is known beforehand. Recent papers investigate the interaction between register allocation and scheduling [71] 72] 2) Data Routing: The above mentioned extension of graph coloring toward heterogeneous register ....

P. Briggs, "Register allocation via graph coloring," Ph.D. dissertation, Rice Univ., Houston, Apr. 1992.

.... [10] page 92) For RISC machines, Chaitin style graph coloring [6] is the dominant approach, as witnessed by its prominence in modern compiler construction textbooks [1, 16, 17] It gives high quality allocations, runs fast in practice, and is supported by a large body of research work (e.g. [5, 8]) Unfortunately, the algorithm assumes a regular register architecture consisting of a single, homogenous set of generalpurpose registers. We propose a generalization of Chaitin s algorithm which allows it to be used with a wide range of irregular architectures, featuring for example register ....

....known to be an NP complete problem, so heuristic techniques are used to perform register allocation in practice. Chaitin et al. 6] presented the first heuristic global register allocation algorithm based on graph coloring. Although it has a worst case time complexity of O(n ) experiments in [5] indicate that in practice it run in less than O(n log n) time. Due to space limitations, we can not give the full algorithm here. For the interested reader, we refer to the description by Briggs [5] or the more elaborate presentation in our technical report [19] 3 Retargetability through ....

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P. Briggs. Register allocation via graph coloring. PhD thesis, Rice University, April 1992.

....reformulations, many of them resulting in significant improvements to the amount of spill code inserted. 10 2. 5 The Briggs allocator We will concentrate on the Briggs allocator in this thesis, because it is widely used and its implementation is clearly laid out in Briggs own dissertation [7]. As a result, we can be confident that other researchers could expect to replicate our results. In the Briggs allocator, there are seven steps, as shown in Figure 2.1. The following is a short synopsis of each step. ffl renumber renames values into live range names, by first converting to ....

....spilling than the original formulation. In 1989, Briggs, Cooper, Kennedy, and Torczon modified the coloring heuristic to be optimistic instead of pessimistic [9] Further enhancements by this team resulted in still more improvements to spilling such as live range splitting and rematerialization [7, 11]. More recent work of particular interest includes George and Appel s work on iterated register coalescing, in which they attempt to reduce the register pressure by folding copy operations during the simplify phase of the compiler [24] Their ideas seem to be only efficacious in specific ....

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Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....support required to use the ccm for spilling can take several forms. We built two di#erent implementations. The first is a post pass ccm allocator that operates after traditional register allocation. The second embeds support for ccm spilling directly into a typical Chaitin Briggs allocator [4]. Our experiments show that the two approaches produce di#erent results. Calculate the call graph (if necessary) 23, 6] Conservatively mark subroutines in call graph cycles as using all of ccm For each subroutine, s, in a postorder walk over the call graph: Rewrite spill instructions with ....

....ccm allocator is invoked after the end of traditional compilation. It takes allocated, scheduled code as input and produces equivalent code where some of the loads and stores inserted for spilling have been redirected into the ccm. It uses the basic algorithms of the Chaitin Briggs allocator [4], but operates over a somewhat di#erent domain. The ccm allocator focuses on spill locations rather than data values in registers. When it runs, all decisions about which live ranges stay in registers have been made. The ccm allocator tries to discover a subset of the spilled values that can be ....

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Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....that value to memory and loading it back when necessary. This technique 64 Split Point (a) Possible Live Range Split by Chow and Hennessy approach Split Point . x y II (b) Preferred live range split Figure 4. 1: Live range splitting is called rematerialization [5] [3]. In other words, rematerialization is a spill re duction technique of replacing spills and reloads with instructions that recompute values that have been evicted from the registers, whenever this is possible and profitable. Figure 4.2 shows an example of rematerialization when there is no ....

.... which may result from using frequency information to determine the split point (where 68 the live range in the loop is not split into two segments) In this case, the shuffle code between two live segments can be move to the less frequent point, the edge E(B3, B4) than E(B2, B3) Briggs [3] also introduced live range splitting into Chaitin style register alloca tion. The splitting points are determined using static single assignment (SSA) 15] representations of programs and the loop boundaries [14] 13] 4] Since live range splitting is performed prior to the coloring phase, the ....

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Preston Briggs. Register Allocation via Graph Coloring. University, April 1992. PhD thesis, Rice

....different optimization techniques since they relate closely to our work with a new design of the back end of the compiler. 5.1 Liveness Analysis This chapter describes liveness analysis applied to languages like Oz and Prolog. Information about a more general liveness analysis can be found in [14, 15, 16, 17, 18, 19]. During register allocation, information about when variables are declared and when they are used for the last time is required. Acquiring this information is called doing Liveness Analysis. Liveness analysis is often done on a set of virtual registers instead of upon the actual variables ....

....often an advantage if an abstraction of the problem can be found, thereby being able to avoid messy details of the original problem and instead concentrate on solving the clean abstracted problem. The register allocation problem can be generalized to the problem of Graph Coloring, see for example [18, 19, 17]. As described in Chapter 5, the liveness of the virtual register set can be seen as a dependency graph G = V,E) where V is a set of vertices (or nodes) depicting the virtual register set, and P a set of edges conforming to the dependencies between the vertices. An edge is an unordered pair (s, ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....large blocks. coalesce: Many of the optimizations insert extraneous copy operations (e.g. common subexpression elimination) Also, an easy algorithm for coming out of SSA form inserts a large number of extra copies. We coalesced them using techniques from graph coloring register allocators [5, 10]. combine: This phase combines logically adjacent instructions into more powerful instructions. This is commonly used to build addressing expressions for LOADs and STOREs. It also performs a variety of peephole optimizations, such as removing two negates in a row. combo: The combined algorithm, ....

P. Briggs, Register Allocation via Graph Coloring. Ph.D. thesis, Rice University, 1992.

....register assignment chooses a speci c register for a speci c value. Register allocation is also used to denote both allocation and assignment. Register assignment is the main concern for people interested in the cooperation with schedulers, so we will focus on register assignment. Graph coloring [28, 26, 42, 23, 22] is the most used technique for register assignment today, incorporating register allocation. Graph coloring works on an interference graph, whereby values (mostly symbolic registers 1 ) represented by nodes, are connected if they have an overlapping liveness interval. Graph coloring tries to ....

Briggs, P. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....is of interest, the goal must be to derive a pattern dependent of loop indices rather than fully unrolling the loop nest. For this reason, a restriction to the innermost loop is made. As the register allocation phase is assumed to be completed, physical registers have to be taken into account [Bri92]. Deriving cache value life times must take place after locality optimizations because they might influence the instruction execution sequence. Figure 4 sketches the cases that can occur. Memory accesses are depicted by full dots, purely register operations by empty dots 3 . Number 1) shows the ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....VR location table accordingly; otherwise do nothing that is, neither generate any machine code nor change the VR location table. To devise an algorithm for determining where swaps should be inserted, we will use the intuition provided by the aggressive live range splitting algorithm of Briggs[6]. There, live ranges are aggressively split before coloring by inserting spill code based upon the single assignment (SSA) form of the method. Extraneous copies are eliminated before coloring is attempted. We will simplify the Brigg s algorithm by simply generating the SSA form and then inserting ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....arrays are represented with UPDATE and REFERENCE operators, respectively. Since we are analyzing Fortran 90D programs, we have enhanced these operators to handle array sections by incorporating regular section descriptors (RSDs) 1] In addition to the SSA graph, we generate an interference graph [3]. The interference graph indicates those SSA variables with overlapping live ranges, and is used to check for violations of criteria 1 or 2. The graph is built in the usual manner, but with one exception: all functions occurring at the same merge point are considered to be executed ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Dept. of Computer Science, Rice University, April 1992.

....of physical registers and the instruction cannot be written back. In this case, the instruction is re executed. 2.3. Register Allocation and Spilling The problem of allocating scalar variables to registers, called the register allocation problem, is usually reduced to a graph coloring problem [Chai81, Chai82, Brig92, Chow84], where an optimal solution is well known to be NP complete. Other research has cast the problem as set of constraints passed to an integer programming solver [Good96, Kong98] or bin packing [Blic92] We focus on graph coloring in this work because it is the most common technique for optimizing ....

....has only the 8 temporary registers the link time technique improves executable speed by 10 to 25 on a configuration with 52 registers. Link time allocation (without dataflow analysis or coloring at all) does better than traditional graph coloring such as is done in a Briggs Chaitin allocator [Chai81, Chai82, Brig92]. Graph coloring can be added in Wall s system in order to allow variables which do not conflict within a procedure to share a register. This local coloring is especially important when there are few registers in the machine but does not improve performance much with 52 processor registers. Our ....

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Preston Briggs. Register Allocation via Graph Coloring.. Rice University, Houston, Texas, USA Tech. Report, 1992.

....phase is symbolic assembly code with references to virtual registers. This code is passed to the register allocator described in the following. B. Register allocation Although the NP shows a RISC like basic architecture, the classical graph coloring approach to global register allocation [26] cannot be directly used. The reason is the need to handle register arrays. As explained in section III (see also Figs. 6 and 8) register arrays arise from indirect addressing in C programs, where unaligned bit packets are traversed within loops. As a consequence, virtual registers containing ....

....the advantages of packet level addressing are naturally lost in exchange for a safe fallback position. After register allocation for the supernodes has been performed, all remaining virtual registers in the original interference graph are mapped to physical registers by traditional graph coloring [26], while inserting spill code whenever required. V. Results The C compiler for the NP described in the previous sections is fully operational. The performance of the generated code has been measured by means of a cycle true NP instruction set simulator for a set of test programs. As may be ....

P. Briggs, \Register Allocation via Graph Coloring," Ph.D. thesis, Dept. of Computer Science, Rice University, Houston/Texas, 1992.

....by a program P, as well as the set of memory banks M of the target architecture. The goal is to find an allocation function alloc : O M that minimizes the execution time of P. 2. 2 Problem complexity Consider the graph coloring problem[16] which has been extensively used in register allocation [4, 2]: given a graph, can its nodes be colored with n colors, provided that only nodes that are not connected by an edge can be assigned the same color Now consider a memory architecture with n memory banks, all of which have waitstate 0 and allow for 1 access per cycle. Moreover, all of them can be ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, Houston, TX, USA, 1992.

....interference graph are computed. Then we present a technique to transform the interference graph to enable better opportunities for coloring in case the coloring scheme blocks. This is followed by an algorithm for allocating configurations which draws from previous work by Chaitin [27, 28] Briggs [19] and Chow and Hennessy [32] 6.5.7 Interference Live range construction. A live range is an isolated and connected group of nodes in the control flow graph that connects the definitions and uses of a given program variable. Live ranges are discovered by finding connected groups of def use ....

....lr into smaller live ranges, each smaller piece spanning a single basic block over which it is live. To decrease the amount of compensation code, adjacent live ranges are combined if the register pressure due to the combined live ranges does not exceed the available number of registers. Briggs [19] in his thesis proposed splitting based on control flow structure. He avoids the problem of picking optimal live ranges and instead chooses split points based on structure of the control flow graph and then splits all live ranges that cross that point. Two of the proposals for split points are ....

Preston Briggs. Register allocation via graph coloring. Phd thesis, Rice University, 1992.

....set restricts allocation to only one of the two banks. As we illustrate later, the Intel x86 ISA exhibits both of these kinds of irregularities. The literature on graph coloring register allocation is not entirely devoid of work on irregular architectures. In particular, Nickerson [9] and Briggs [2,3] both describe approaches that adapt graph coloring based allocators for regular architectures to a limited class of irregular architectures. These authors realized that the kinds of irregularities described above directly affect a graph coloring allocator s interpretation of its interference ....

....with this implementation, and we describe our on going work exploring the effects of modeling precision. Finally, Section 7 discusses related work, and Section 8 offers our conclusions. 2 Allocation by Graph Coloring Figure 1 decomposes the graph coloring register allocator proposed by Briggs [3] into its constituent phases and illustrates the algorithmic flow between these phases. We focus our discussion on optimistic allocators because, as Briggs argues, the optimistic coloring heuristic produces better allocations than the pessimistic heuristic used by Chaitin [5] Furthermore, the ....

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P. Briggs. "Register Allocation via Graph Coloring," Technical Report CRPC-TR92218, Center for Research on Parallel Computation, Rice University, Houston, TX, April 1992.

....Scheduler Bwd Inst Scheduler Bwd Cyc Figure 7: Hierarchy of scheduler classes. There exist a number of approaches to graph coloring based register allocation; for example, Chaitin style coloring [7, 2] optimistic coloring [4] priority based coloring [9] and several modern approaches [3, 5, 27, 24] that take the program structure into account when splitting live ranges. It is difficult and impractical to implement and experiment with these different register allocation approaches without a register allocation framework. In addition, a framework facilitates a fair comparison; that is, if an ....

....based, whereas the other is priority based. In addition, this framework can also model other approaches to live range splitting that take the program structure into account, such as the approaches taken by Tera [5] Multiflow [11] and RAG [27] as well as splitting based on the SSA representation [3], and the integrated approach to splitting and spilling provided by fusion style coloring [24] A more detailed discussion of these approaches can be found in a technical report [24] The class hierarchy of the register allocation framework is depicted in Figure 9. There are two classes: 1) ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....are removed. Color assignment blocks when no legal color exists for a live range lr to be colored, i.e. when all N colors have been taken up by lr s neighbors. At this point, lr is split. Larus and Hilfinger implement the priority based approach in the SPUR Lisp compiler [25] Briggs s thesis [3] uses the Static Single Assignment (SSA) representation of a program to determine splitting points, and splitting live ranges takes place prior to coloring. A live ACM Transactions on Programming Languages and Systems, Vol. XX, No. X, XXXX, 199X. Fusion based register allocation Delta 5 range is ....

....approaches [6; 34; 13; 32; 35] reduce shuffle cost by prioritizing a function into regions and thereby perform register allocation in a hierarchical manner, so the shuffle code is placed in less important regions. Others [3; 6; 34; 13] rely on some similar techniques such as biased coloring [3] to eliminate a shuffle move by assigning the same color to the two live ranges that the move connects. 2.3 Shortcomings of prior work The main problem of Chaitin style simplification is that the spilling decisions are all ornothing: all definitions and uses of a spilled live range go through ....

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P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....Perfectly Nested Loop The single definition of a read only variable can either occur within the loop or outside of the loop. The read only region associated with the definition of a read only array is the part of the program for which the read only value is life, i.e. is its life range [Bri92] The definition of a read only array dominates all uses of the array in the PCFG. Read only regions of different arrays may overlap, resulting in potential conflicts where not all desired copies may fit into the available memory. All arrays referenced in the loop body are classified as ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....very high degree, so no conservative coalescing was possible. Iterated register coalescing guarantees to keep a colorable graph colorable, but it cannot find the optimal set of nodes to spill in an uncolorable graph. There has been much research on shrinking and splitting of live ranges [LGAT97, Bri92, CH90a, LH86] but some of these approaches are quite complicated and it was not clear how best to integrate them with graph coloring for architectures with few registers where large amounts of spilling and splitting may be involved. In the last few years some researchers have taken a completely ....

....single assignment (SSA) form, which divides each program variable into several temporaries based on the relation of definitions of the variable to the dominator tree of the program. Then a Chaitin style spiller implements each temporary either entirely in registers or entirely in memory. Briggs [Bri92] conjectured that SSA was the best way to split the variables prior to coloring with coalescing. Our current paper can be viewed as a test of his conjecture; we have described an entirely different method for splitting the variables. A characteristic of SSA form is that there will typically be ....

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Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....simple loop. Swift also gives lower weight to edges that leave a trace in the middle, since these edges have already been determined to be less important than the remaining edges in the trace. 3.4. 3 Register Allocation The register allocator in Swift is a modified Briggs style coloring allocator [7]. Our allocator is novel in that it does not use coalescing, but instead uses a special data structure, the 18 WRL Research Report 2000 2 The Swift Java Compiler: Design and Implementation bias graph, to direct coloring and limit the number of copies introduced. Register allocation proceeds by ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, Apr. 1992.

....has only the 8 temporary registers the link time technique improves executable speed by 10 to 25 on a configuration with 52 registers. Link time allocation (without dataflow analysis or coloring at all) does better than traditional graph coloring such as is done in a Briggs Chaitin allocator [15, 16, 17]. Coloring can be added in Wall s system in order to allow variables which do not conflict within a procedure to share a register. The Sparc architecture s register windows are a hybrid register memory architecture intended to optimize function calls [3, 18] Each subroutine gets a new window of ....

Preston Briggs. Register Allocation via Graph Coloring.. Rice University, Houston, Texas, USA Tech. Report. unknown month, 1992.

....coordinates are linear functions of s and t or vertex coordinates, they are recognized as a single pass with some combination of texture coordinate generation and texture matrix. Texture memory utilization is minimized by allocating storage based on single static assignment and live range analysis [4]. 4.3 Demonstration We have implemented a RenderMan renderer, complete with shading language, bytestream, and procedural interfaces on a software implementation of OpenGL including color range and pixel texture. We experimented with subsets of IEEE single precision floating point. An interesting ....

BRIGGS, P. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....These sets are empty at the beginning of register allocation and are updated during the introduction of spill code. For each pointer containing register that is live across a function call and is being spilled, the corresponding stack location is added to to the set for the function call. 9 See [Bri92] for a detailed description of when this can be done. 12 6 Runtime Support The majority of the runtime system code is written in Java, both for convenience and to provide a large, complex test case for the Marmot compiler. Operations including cast, array store and instanceof checks, ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....that neighboring nodes have different colors. By choosing k to match the number of architectural registers, a k coloring will represent a feasible allocation of live ranges to registers. An optimal allocation is not feasible, because the problem of finding a k coloring with k 3 is NP complete [Briggs 1992]. Heuristic techniques are used to rank the nodes so that the higher priority ones are colored first, and to select a live range to be spilled should there be no color available for a node. Should spilling be necessary, the graph is modified, and another attempt is made at coloring it. This ....

....ranges that include boundary points are said to be boundary live ranges. Thus, unlike in some compilers, a copy operation is not introduced at the entry or exit point of procedures to permit boundary live range to occupy a register that is not live on entry or on exit; the reader is referred to [Briggs 1992] for an example in which such copies are used. The register allocation of boundary live ranges is done by the schedulers in the initialization phase (see the discussion of Figure A.3) A.2.3 Partitioning the Live Ranges The live ranges that are neither a boundary live range nor a candidate for a ....

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Briggs, P. (1992). Register Allocation via Graph Coloring. PhD thesis, Department of Computer Science, Rice University, Houston, Texas.

....to correctly allocate ambiguously aliased object to CRegs. Globals are not allocated and so are pre spilled which means that for each USE DEF there is spill code responsible for loading storing the value. Live ranges for scalar locals and formal parameters are created as described by Briggs [Bri92]. 3.2 Alias Analysis This section describes how we group objects into alias sets in preparation for allocating them to CReg sets. If ambiguously aliased objects were not grouped in alias sets, they might be allocated across multiple CReg sets and stale data could occur in some CRegs. The alias ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....insert the necessary loads and stores and go to step 2. 10 2.6.3 Briggs allocator This is a refinement of Chaitins scheme, based on optimistic graph coloring and rematerialization. Optimistic graph coloring was originally presented by Matula and Beck [23] and subsequently developed by Briggs [7, 6, 5]; the idea is that of postponing the spill decision until the selection phase. Thus, if there is no node in the graph with degree less than the number of registers, a node is chosen for spilling, like in Chaitins allocator, but it is pushed on the stack just like nodes with lesser degree. This ....

Preston Briggs. Register allocation via graph coloring. PhD Thesis Rice COMP TR92183, Department of Computer Science, Rice University, 1992.

....are made. When a coalesced node is to be actually spilled in the select phase, we attempt to reduce the spill cost of the node using a technique called live range splitting. Live range splitting is a technique for reducing the spill amount which has been employed by many optimizing compilers [2, 3, 9, 10, 11, 12]. It splits a long live range into shorter ones by inserting copies and load stores at appropriate places in the code. Live range splitting may obviate spills since shorter live ranges are more likely to be colored than longer ones. The cost involved is the additional instructions inserted for ....

....the allocator cannot avoid the spill completely with live range splitting, the spill amount can be reduced because it is possible to color some splits while spilling other splits. Unfortunately, live range splitting in global register allocation is not straightforward to do due to several reasons [12, 13], among which the primary one is the difficulty in deciding where to insert the splitting instructions. In our context of reducing the spill cost of a coalesced node by live range splitting, it is straightforward where to insert the splitting copy: the original location where the coalesced copy ....

P. Briggs. Register allocation via graph coloring. PhD thesis, Rice Univ., Apr. 1992.

....merge only accounts for a small portion ( 10 in our experience) of the if converted compare instructions. In the future, we will model comparison instructions with an or type more precisely. 5 Predicate aware Register Allocation The problem of global register allocation is well known [4, 5, 6] and good heuristic approximations have been developed to solve the problem. However, predication creates new challenges for the established techniques. In the quest for greater instruction level parallelism through predication many register live ranges are created which, with current analysis ....

Preston Briggs, Register Allocation via Graph Coloring, Ph.D Thesis, TR92-183, Rice University, 1992.

....allocation by Sites and Perkins [2] Techniques for global register allocation have been extensively studied. The most notable work in the area of function level global register allocation via graph coloring has been done by Chaitin et al. 3] Chow and Hennessy [4] and more recently by Briggs [5]. A slightly different approach using hierarchical graph coloring has been proposed by Callahan and Koblenz [6] Although this thesis will focus on intraprocedural allocation, several examples of work in the area of interprocedural or program level global register allocation are work by Chow [7] ....

....of r3 and r6 graph is no longer correct and must be rebuilt. The interference graph construction and coalescing steps are repeated until there are no more live ranges that may be coalesced. In practice, it has been shown that this process will converge within 2 to 3 iterations [3] 12] [5]. 2.1.3 Spill costs Now that the interference graph is stable, a spill weight is calculated for each remaining live range. Chaitin s register allocator assigns a weight to each live range that represents the cost of spilling it, which is the cost of executing the loads and stores that must be ....

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P. Briggs, Register Allocation via Graph Coloring. Ph.D. dissertation, Department of Computer Science, Rice University, Houston, TX, 1992.

....use them. Status: implementation finished, paper in progress Reassociation We published an algorithm for using commutativity and associativity to improve optimization of integer expressions. It produces improvements of up to 40 in the running time of optimized scientific Fortran code [2]. Status: implemented, published Scheduling We have developed an estimator that can be used in Lam s software pipelining algorithm to make the choice of an initial kernel length (or initiation interval) sensitive to demand for registers [5] The computation plugs directly into Lam s algorithm ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....block v, only those operations that affected the Live set are undone, so that at the bottom of v the Live set is precisely equal to what it started as. 4 Applications of Liveness 4. 1 Interference Graph Construction Most modern compilers perform register assignment with graph coloring algorithms [1, 11]. An interference graph is constructed, such that G IG = hS; Ei, where S is the set of symbols in the program and E is a set of edges such that (r; s) 2 E iff r interferes with s, that is, if r and s are simultaneously live at any point in the program. The nodes in the graph are then colored , ....

Preston Briggs. Register allocation via graph coloring. PhD Dissertation COMP TR92-183, Rice Univ., Dept. Computer Science, April 1992.

....how to tune RoD using several heuristics. Section 6 evaluates the results of the performed experiments. The final section gives the conclusions. 2 Related work Most methods for global register allocation are based the work of Chaitin [6, 7] a number of improvements are published later on [8]. All these methods are based on graph coloring. Consequently, they assume that operations do not move relative to one another. However, in the presence of instruction scheduling, this could be a wrong assumption. Lately some work is done on the interaction between the instruction scheduling and ....

....combines the information from the parallel code with the profiling data in order to obtain dynamic information such as the cycle count. The results are compared with two early assignment approaches. The first early assignment approach is a standard optimistic register allocator as described in [8], which we will call standard early assignment or in short SEA. The second approach uses also the optimistic register allocator but it uses also data dependence information. Doing this will reduce the chance of introducing false dependences. This method is described in [11, 10, 9] we will call ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

.... Procedure cloning or inlining may be applied under certain conditions to improve context for optimization [HKT91, HKT92, HHKT91, Tse93] Node compilers may perform optimizations to exploit the memory hierarchy and instruction level parallelism available on the target node processor [Car92, Wol92, Bri92] At present, the principal target of our prototype Fortran D compilation system [Tse93] is the Intel iPSC 860. Eventually, the compilation system will target a variety of distributedmemory multiprocessors such as Intel s iPSC 860 and Paragon, Ncube s Ncube 1 and Ncube2, and Thinking Machine ....

P. Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....Graph [WCES94] and our algorithm could improve the complexity of constructing these related intermediate representations. Also there are many optimizations that use SSA form for efficient implementation, for example, constant propagation [WZ85] value numbering [RWZ88] register allocation [Bri92] code motion [CLZ86] etc. Our algorithm could improve the overall running time of these optimizations. In this paper we have employed a new program representation the DJ graph. Derived from a flowgraph, the DJ graph can be viewed as a refinement representing explicitly and precisely both ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, Houston, Texas, April 1992.

....number of live ranges (also known as pseudoregisters) for the variables and temporary values of the program. The task of register allocation is to map these live ranges onto a finite register set. The standard approach to register allocation is graph colouring [CAC 81, Cha82, BCKT89, CH90, Bri92b] As the basis for dependence conscious colouring, we used the algorithm presented in [BCKT89] Figure 2 presents the phases of a graph colouring register allocator. conventional colouring with postpass scheduling preordered intermediate code build interference graph order nodes colour nodes ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, Houston, 1992.

....is of interest, the goal must be to derive a pattern dependent of loop indices rather than fully unrolling the loop nest. For this reason, a restriction to the innermost loop is made. As the register allocation phase is assumed to be completed, physical registers have to be taken into account [Bri92]. Deriving cache value life times must take place after locality optimizations because they might influence the instruction execution sequence. Figure 4 sketches the cases that can occur. Memory accesses are depicted by full dots, purely register operations by empty dots 5 . Number 1) shows the ....

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

....shown to be an NP complete problem [6] Therefore, it is impractical to find the optimal solution. Several heuristics are available that perform well in practice. However, commonly used heuristics have a problem that they have no way to encode the program structure in the interference graph [2] 3][4]. Program structure is used to represent sections of a function that have different execution frequency like loops or conditional structures. Without the information of program structure, poor spill decisions can be made. For example, without the knowledge of a loop boundary, spill code can be ....

....in Section 2.1, is the commonly used mechanism for register allocation. Since graph coloring problem is an NP complete problem, heuristics are needed to find a practical solution. Several commonly used heuristics are detailed. Section 2.2 describes Chaitin s[2] method, Section 2. 3 presents Briggs [4] method, Section 2.4. presents Chow s[3] method. Finally, the common problem with all these methods is presented in Section 2.5. 2.1 Graph Coloring Register Allocation Register allocation is commonly treated as a graph coloring problem. An interference graph for a function is a graph in which a ....

Preston Briggs. Register Allocation via Graph Coloring. Ph.D. thesis, Rice University, 1992.

....reformulations, many of them resulting in significant improvements to the amount of spill code inserted. 10 2. 5 The Briggs allocator We will concentrate on the Briggs allocator in this thesis, because it is widely used and its implementation is clearly laid out in Briggs own dissertation [7]. As a result, we can be confident that other researchers could expect to replicate our results. In the Briggs allocator, there are seven steps, as shown in Figure 2.1. The following is a short synopsis of each step. renumber renames values into live range names, by first converting to SSA form ....

....spilling than the original formulation. In 1989, Briggs, Cooper, Kennedy, and Torczon modified the coloring heuristic to be optimistic instead of pessimistic [9] Further enhancements by this team resulted in still more improvements to spilling such as live range splitting and rematerialization [7, 11]. More recent work of particular interest includes George and Appel s work on iterated register coalescing, in which they attempt to reduce the register pressure by folding copy operations during the simplify phase of the compiler [24] Their ideas seem to be only efficacious in specific ....

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Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice Uni- versity, April 1992.

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Preston Briggs, `Register allocation via graph coloring', Ph.D. Thesis, Rice University, April 1992.

....stores inserted after definitions. Splitting. The final column shows code we would expect from a splitting allocator [11, 27, 23, 5] the actual code might be worse. In fact, our work on rematerialization was motivated by problems observed during our own experiments with live range splitting [3]. Unfortunately, examples of this sort are not discussed in the literature on splitting allocators and it is unclear how best to extend these techniques to achieve the Ideal solution. This section divides into two major subsections. The first presents a conceptual view of our approach to ....

....unproductive copies. 3 Note that the allocator could insert all the copies suggested in the Splits column as a form of live range splitting. We are currently exploring the problem of performing live range splitting in a Chaitin style allocator. So far, our experimental results have been mixed [3]. ACM Transactions on Programming Languages and Systems, Vol. 16, No. 3, May 1994, pp. 428 455. Improvements to Graph Coloring Register Allocation 13 4.2 Implementing Rematerialization Chaitin style allocators can be extended naturally to accommodate our approach. The high level structure ....

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Briggs, P. Register Allocation via Graph Coloring. PhD thesis, Rice University, Apr. 1992.

....are possible, each offering different advantages. The choice of a best representation for a given set depends on the operations required, their cost in both time and space, and the relative frequency of those operations. As a part of our exploration of register allocation via graph coloring [4, 7], we looked for good implementations for each phase of the allocator. To quickly construct the interference graph, we needed a set representation that supported efficient implementations of the operations clear set, add member, and delete member, as well as an iterator, forall, that enumerated the ....

....an experimental comparison of two implementations. We also describe briefly several other successful applications of sparse sets. 4. 1 Constructing an Interference Graph Our original motivation was efficiently constructing the interference graph for use during graph coloring register allocation [6, 4]. The interference graph construction algorithm is sketched below. In this setting, we are concerned with the operations involving the set live. for each block b in the flow graph f clearset(live) 1) for each live range lr in b liveOut addmember(live, find(lr) 2) for each instruction i in ....

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Briggs, P. Register Allocation via Graph Coloring. PhD thesis, Rice University, Apr. 1992. 9

....and stores inserted after definitions. Splitting The final column shows code we would expect from a splitting allocator [11, 25, 21, 5] the actual code might be worse. In fact, our work on rematerialization was motivated by problems observed during our own experiments with live range splitting [3]. Unfortunately, examples of this sort are not discussed in the literature on splitting allocators and it is unclear how best to extend these techniques to achieve the Ideal solution. This section divides into two major subsections. The first presents a conceptual view of our approach to ....

....isolated and no further copies have been introduced. The algorithm for removing OE nodes and inserting copies is described in Section 4.2. Of course, the allocator could insert all the copies suggested in the Splits column as a form of live range splitting. This idea has been discussed elsewhere [3]. Removing Unproductive Splits Our approach inserts the minimal number of copies required to isolate the never killed values. Nevertheless, coloring can make some of these copies superfluous. Recall the Minimal column in Figure 6. If neither p 0 nor p 12 are spilled and both receive the same ....

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Briggs, P. Register Allocation via Graph Coloring. PhD thesis, Rice University, Apr. 1992.

....and a variety of traditional optimizations [9] We currently generate code for the IBM RT PC and have experimental code generators for the Sparc, i860, and RS 6000. To experiment with register allocation, we have built a series of allocators that are independent of any particular architecture [2]. Our experimental allocators work with routines expressed in ILOC, a low level intermediate language designed to allow extensive optimization. An ILOC routine that assumes an infinite register set is rewritten in terms of a particular target register set, with spill code added as necessary. The ....

....be slightly faster than the times reported by IBM s xlf compiler for register allocation and comparable to the times reported for optimization. In an extensive comparison with prioritybased coloring, our allocators appeared much slower on very small routines, but much faster on very large routines [2]. Of course, these speeds are not competitive with the fast, local techniques used in non optimizing compilers [14, 15] however, we believe that global optimizations require global register allocation. 6 Extensions Of course, rematerialization is not the only reason for splitting live ranges; ....

[Article contains additional citation context not shown here]

Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

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P. Briggs. Register allocation via graph coloring. Technical Report CRPC-TR92218, Rice University, Houston, TX, April 1992.

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P. Briggs. Register allocation via graph coloring. Technical Report CRPC-TR92218, Rice University, Houston, TX, April 1992.

No context found.

Preston Briggs. Register Allocation via Graph Coloring. Technical Report TR92-183, Rice University, 24, 1992.

No context found.

Preston Briggs. Register allocation via graph coloring. Phd thesis, Rice University, 1992.

No context found.

Preston Briggs, `Register allocation via graph coloring', Ph.D. Thesis, Rice University, April 1992.

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Preston Briggs. Register Allocation via Graph Coloring. PhD thesis, Rice University, April 1992.

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