L. Pierre. From a HDL Description to Formal Proof Systems: Principles and mechanization. In [6], pages 1--21.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....as ELLA, the logical terms representing ELLA expressions in HOL gets voluminous and hard to use, thus making reasoning unnecessary difficult. The other approach is to define new HDL s with formally defined semantics (see [28] for a general discussion) Examples of this approach can be found in [21, 53, 56, 58, 70, 80, 84, 89]. Basically, a design logic is also a formal HDL. 2.3 Formal Digital System Design In this section we introduce and discuss formal system design. We start by relating it to the concepts of design and formal verification. It is fair to say that formal digital system design has developed from ....

L. Pierre. From a HDL Description to Formal Proof Systems: Principles and mechanization. In [6], pages 1--21.

....function is itself not part of hol, the case statement is informal and the variable in has no explicit relation to in (cf. Equation 1) Other related work includes [79, 25] which describe mapping vhdl into hol and sdvs respectively. silage has also been given a hol semantics as above [34, 2] In [63] behaviours of cascade descriptions are mapped into the BoyerMoore and tache theorem provers. Eveking uses the lovert system to check the equivalence of smax hdl circuit descriptions [23, 24] Recently Umbreit has used Lambda to map vhdl programs onto formally defined ml descriptions [77] Formal ....

Laurence Pierre. From a HDL description to formal proof systems: Principles and mechanization. In D Borrione and R Waxman, editors, CHDL 91: 10th International Symposium on Computer Hardware Description Languages and Their Applications, April 1991.

....Equation 2.4 on page 19. 19,17] go into some detail describing the semantics of ella, which we will comment on in Section 4.2.4. Other related work includes [174,56] which describe mapping vhdl into hol and sdvs respectively. silage has also been given a hol semantics in this manner [75,2] In [145] the Boyer Moore and tache theorem provers are used as the target logics to map behaviours of cascade descriptions into. Eveking uses the lovert system to check the equivalence of smax hdl circuit descriptions [54,55] Recently Umbreit has mapped vhdl programs onto ml descriptions using the ....

Laurence Pierre. From a HDL description to formal proof systems: Principles and mechanization. In D Borrione and R Waxman, editors, CHDL 91: 10th International Symposium on Computer Hardware Description Languages and Their Applications, April 1991.

.... of the approach used to solve the dining philosophers problem in [17] The Min Max signal processor unit was formulated as a benchmark problem for the 1989 IFIP International Workshop on Applied Formal Methods for Correct VLSI Design [8] Here we study a parameterized version suggested in [26]. This version was specified in the CASCADE Hardware Description Language and verified by means of a theorem prover. We argue that such descriptions can be straightforwardly translated into Mona provided that the arithmetic used is essentially regular. The unit is controlled by three Boolean ....

....the parameterized adder is stated to last approximately 2 minutes (as opposed to our time of one second) and their proof of the ALU required 90 seconds, as opposed to 2 seconds in our case. 29 The signal processor circuit was verified in NQTHM (the Boyer Moore theorem prover) and reported on in [26]. The proof required the user to formulate various lemmas. Even with the lemmas, verification required several minutes of CPU time, as opposed to 10 seconds in our case. These examples suggest that when a parameterized system is formalizable in M2L, then there can be real advantages with our ....

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L. Pierre. From a HDL description to formal proof systems: Principles and mechanization. In Proceedings of CHDL'91, Marseille France, pages 21--42. IFIP Transactions, North-Holland, April 1991.

....and 12,865 BDD nodes. 7 A Parameterized Benchmark: the Min Max Circuit The Min Max signal processor unit was formulated as a benchmark problem for the 1989 IFIP International Workshop on Applied Formal Methods for Correct VLSI Design [7] Here we study a parameterized version suggested in [25]. This version was specified in the CASCADE Hardware Description Language and verified by means of a theorem prover. We argue that such descriptions can be straightforwardly translated into Mona provided that the arithmetic used is essentially regular. The unit is controlled by three Boolean ....

....of the parameterized adder is stated to last approximately 2 minutes (as opposed to our time of one second) and their proof of the ALU required 90 seconds, as opposed to 2 seconds in our case. The signal processor circuit was verified in NQTHM (the Boyer Moore theorem prover) and reported on in [25]. The proof required the user to formulate various lemmas. Even with the lemmas, verification required several minutes of CPU time, as opposed to 10 seconds in our case. These examples suggest that when a parameterized system is formalizable in M2L, then there can be real advantages to our ....

L. Pierre. From a HDL description to formal proof systems: Principles and mechanization. In Proceedings of CHDL'91, Marseille France, pages 21--42. IFIP Transactions, North-Holland, April 1991.

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