Mich`ele Dion, Tanguy Risset, and Yves Robert. Resource-constrained scheduling of partitioned algorithms on processor arrays. Integration, the VLSI Journal, 20:139--159, 1996. Home/Search Document Details and Download
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Determination of the Processor Functionality in the Design of .. - Fimmel, Merker (1997) (Correct)
....of the MPPA design is to minimize the latency, i.e. the total execution time, of the processor array. Recent approaches connect the syntheses of processor arrays with the high level syntheses by including hardware constraints in the determination of the scheduling and the allocation function [3, 7, 16, 18, 19]. The work of Thiele [19] represents the basis of this paper. Here an integer linear program is formulated to search a scheduling function minimizing the latency of the processor array and satisfying a limited number of functional resources (modules) realized in the processors. In our approach we ....
M. Dion, T. Risset, Y. Robert: "Resource-constrained Scheduling of Partitioned Algorithms on Processor Arrays", Research Report No. 94-19, LIP-ENS Lyon, June 1994
Optimal Task Scheduling to Minimize Inter-Tile Latencies - Rastello, Rao, Pande (1998) (Correct)
....different permutations of tasks in individual tiles. Our framework is able to handle constant but compile time unknown dependences by generating optimal task permutations at run time and results in significantly lower loop completion times. Our solution is an improvement over previous approaches [2, 6] and is optimal for all problem instances. We also propose efficient algorithms that provide the optimal solution. The framework has been implemented as an optimization pass in the SUIF compiler and has been tested on a distributed memory system using a message passing model. We show that the ....
....among processors in order to improve data locality thereby addressing the issue of memory to tile latencies. On the other hand, we perform loop tiling and attempt to minimize inter tile latencies by re ordering individual tasks within a tile. Previous approaches by Chou Kung [2] and Dion et al. [6] to the problem of finding an optimal task ordering within loop tiles have relied on heuristics that do not yield the optimal solution for all instances of the problem even in one dimension. Thus, finding the optimal solution in one dimension is still an open issue. The central contribution of ....
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M. Dion, T. Risset, and Y. Robert. Resource-constrained Scheduling of Partitioned Algorithms on Processor Arrays. In Proceedings of Euromicro Workshop on Parallel and Distributed Processing, pages 571--580, 1995.
Tiling With Limited Resources - Calland, Dongarra, Robert (1997) (4 citations) Self-citation (Yves) (Correct)
....entities that are mapped to processors. Communications can occur as soon as the data is available, while processing the last computational points of the current tile. Each tile still executes the same program, up to a translation in time. This approach has been chosen by several authors, including [9, 8, 7, 20, 10, 19]. In several of these papers, resource constraints on the number of communication links and the fixed topology of the communication network are introduced, leading to solving complex optimization problems via Integer Linear Programming (ILP) techniques. We do not present further details of these ....
Mich`ele Dion, Tanguy Risset, and Yves Robert. Resource-constrained scheduling of partitioned algorithms on processor arrays. Integration, the VLSI Journal, 20:139--159, 1996.
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