Burch J. R., Clarke E. M., McMillan K. L. and Dill D. L. [1990], Sequential circuit veri cation using symbolic model checking, in `Proc. 27th ACM/IEEE Design Automation Conference (DAC '90)'.  Home/Search   Document Not in Database   Summary   Related Articles   Check

....for V # (V ) We shall call v = N# the next state relation for v. Using the partitioned transition relation, the pre image of a state predicate S(V ) denoted by pre(S(V ) can be computed using the following relational product algorithm utilizing early variable quanti cation ([4, 8]) pre(S(V ) #V # )# ( R# (V;V # :S(V ) where S(V ) is obtained from S(V ) by substituting each variable v # V with its next version v # V . Adrawback with this algorithm is that it involves the entire partitioned transition relation ....

J. Burch, M. Clarke, K. McMillan, and D. Dill. Sequential circuit veri cation using symbolic model checking. In DAC'99, 1990.

....cient data structure used for representing and manipulating boolean expressions : they use less space than the traditional methods, and provide mostly linear algorithms to operate over the expressions. BDDs have been used for the veri cation and synthesis of combinational and sequential circuits [5, 4]. One important aspect of these techniques is the reachability analysis, that is, computing the characteristic function of all the states of the system that are reachable from a given (set of) initial con gurations. It involves a breadth rst search that consists in iteratively calculating the ....

J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential circuit veri cation using symbolic model checking. In 27th DAC, 1990.

.... for checking behavioral equivalence when the functional behavior of circuits as boolean functions is abstracted [7, 8] Model checking techniques have been found useful for nding bugs in protocols, particularly cache coherence protocols for caches and memory, as well as protocols for networks [10, 11]. Like any methodology, OBDDs and model checking approaches have their own limitations. For instance, OBDDs cannot be used for verifying even simple arithmetic circuits such as multipliers, SRT division, and oating point arithmetic circuits; extensions to OBDDs in the form of OBMDs [8] as well ....

.... [26] we have developed methods for automatically generating lemmas needed in proving properties from the descriptions [28] In memory modeling and processor veri cation, the quanti er free theory of equality with uninterpreted symbols is getting used within the model checking CAV community [10]. There were at least three papers on this topic in the 1999 CAV conference [12] Presburger theory of numbers has also been found useful in reasoning about arithmetic circuits. Dill s group has developed heuristics for establishing properties over bit vectors and their number representations ....

J. R. Burch, E. M. Clarke, K. L. Mcmillan and D. L. Dill, \Sequential circuit verication using symbolic model checking," Proc. 27th ACM/IEEE Design Automation Conference, 1990.

....of our solution formulas. The iterative interpretation of quantitative game calculus leads to algorithms for the computation of approximate solutions. By representing value functions symbolically, these algorithms may be used for the approximate analysis of games with very large state spaces [3, 7]. Unfortunately, except for safety and reachability conditions, the alternance of least and greatest xpoint operators in the solution formulas leads to approximation schemes that do not converge monotonically to the value of a game. This situation contrasts with the one for Markov decision ....

J. Burch, K. McMillan, E. Clarke, and D. Dill. Sequential circuit verication using symbolic model checking. In Proc. of the 27th ACM/IEEE Design Automation Conference, pages 46-51, Orlando, FL, USA, June 1990.

.... based on Binary Decision Diagrams (BDDs) 1, 8] are the state ofthe art approach, avoiding an explicit representation of state sets [15, 5, 18] Basically, there are two methods to compute the set of reachable states: one uses Transition Functions [7] the other uses Transition Relations [2]. Recently, a method to combine both approaches has been presented [18] In this paper, we restrict to the latter approach. There are two common ways to improve reachability analysis: the rst one is based on partitioned transition relations [23, 3, 6, 4, 19] the second one uses partial and ....

.... of image computations that terminates as soon as no new states can be reached, i.e. New(x) see Figure 1 for a sketch) To obtain the image of a set S B n of states, the relational product has to be computed, f(S) y) 9x: TR f (x; y) S(x) which can be carried out in one pass on BDDs [2], allowing signi cant reductions in runtime and space requirements. Replacing the variables y by x to compute To(y)j y x can be done by calling a substitution algorithm for all variables. B. Linearly Transformed BDDs De nition 2 A Linear Transformation of a set of (input) variables z = fz 1 ; ....

J.R. Burch, E.M. Clark, K.L. McMillan, and D.L. Dill. Sequential circuit verication using symbolic model checking. In Design Automation Conf., pages 46-51, 1990.

....functions appearing in practice can be compactly represented. 3) There are ecient algorithms for many Boolean operations on OBDDs. As a result of these properties, OBDDs are widely used for various applications, especially in computer aided design and veri cation of digital systems (see e.g. [4, 14]) The manipulation of knowledge bases by OBDDs (e.g. deduction and abduction) was rst discussed by Madre and Coudert [10] We rst compare the above three representations, i.e. formula based, model based, and OBDD based, on the basis of their sizes. In particular, we show that, in some cases, ....

J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill, \Sequential Circuit Verication Using Symbolic Model Checking," in Proc. of 27th ACM/IEEE DAC, pp.46-51, 1990.

....instantly for the bitonic sort of 4 elements saying that the sort algorithm is correct. 6 Example 2: Microprocessor Veri cation As a second example of the use of SVC in Haskell, we present the veri cation of a simple pipelined ALU used in Burch and Dill [7] originally found in Burch et al. [6]) In their presentation, they use a simple hardware description language based on Lisp as input to their veri cation process. This section describes how this example can be veri ed in Haskell using SVC and uninterpreted functions for the datapath operations. The Burch and Dill approach to veri ....

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. Dill. Sequential circuit verication using symbolic model checking. In DAC, 1990.

....to make Reachability Analysis applicable for large designs. Especially symbolic techniques which avoid an explicit representation of the set of reachable states and of the FSM transition relation by using BDD representations increased the problem sizes which could be solved by FSM traversal [8, 11, 13, 3]. In order to reduce time and memory consumption for circuits with realistic sizes, several improvements of the basic symbolic FSM traversal techniques have been proposed. To avoid huge BDD representations of monolithic transition relations for large FSMs, decomposition has been used: conjunctive ....

J.R. Burch, E.M. Clark, K.L. McMillan, and D.L. Dill. Sequential circuit verication using symbolic model checking. In Design Automation Conf., pages 46-51, 1990.

....Analysis applicable for large designs. Especially symbolic techniques which avoid an explicit representation of the set of reachable states and the FSM Transition Relation (TR) by using BDD representations increased the problem sizes which could be solved by FSM traversal to a large extent [8, 9, 13, 3]. In order to reduce time and memory consumption for circuits with realistic sizes, several improvements of the basic symbolic FSM traversal techniques have been proposed. To avoid huge BDD representations of monolithic TRs for large FSMs, decomposition has been used: conjunctive partitioning for ....

J.R. Burch, E.M. Clark, K.L. McMillan, and D.L. Dill. Sequential circuit verication using symbolic model checking. In Design Automation Conf., pages 46-51, 1990.

....succeed on examples larger than the standard backwards traversal can handle, and even in many cases where both methods succeed it is shown to be faster. 1 Introduction The range of systems that can be formally veri ed has improved drastically since the introduction of symbolic model checking [7, 8] with the use of reduced and ordered binary decision diagrams (ROBDD) in the eighties [3, 2] Since then many people have improved on the basic algorithms by introducing more ecient techniques, more compact representations and new methods for simplifying the models. One way to do simpli cations ....

.... [ E( 1 U 2 ) U S: 2 ] 1 ] EX] U) Here we use x:f(x) and x:f(x) as the maximal and minimal xed points of a monotone function f on a complete lattice, as given by Tarski s xed point theorem [16] The rest of the operators can be de ned using the above operators [8]. 4 Bounded CTL Solutions In this section we introduce the bounded CTL solution. A bounded CTL solution consists of two sets of states, namely L[ I and U [ I which are lower and upper approximations to the solution of the formula. The idea is to test for inclusion of the initial state in ....

J.R. Burch, E.M. Clarke, K.L. McMillan, and D.L. Dill. Sequential Circuit Veri- cation Using Symbolic Model Checking. In Proceedings of the 27th ACM/IEEE Design Automation Conference, pages 46-51, Los Alamitos, CA, June 1990. ACM/IEEE, IEEE Society Press.

....much user guidance from specialized experts. Some interesting results have been obtained using more automatic techniques [18, 13] but they do not verify operative parts of processors. Therefore they cannot perform functional verications of complex arithmetic circuits. Completely automatic methods [20, 12, 5] are lacking for abstraction mechanisms and so generally focus on proving low level descriptions. The problem of combining automation and high level proofs with abstraction is not limited to processor verication but also extends to several circuits and protocols. Some researchers solved this ....

J. Burch, E. Clarke, K. McMillan, and D. Dill. Sequential circuit verication using symbolic model checking. In 27 th ACM/IEEE Design Automation Conference, 1990.

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Burch J. R., Clarke E. M., McMillan K. L. and Dill D. L. [1990], Sequential circuit veri cation using symbolic model checking, in `Proc. 27th ACM/IEEE Design Automation Conference (DAC '90)'.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit veri cation using symbolic model checking. In 28th Design Automation Conference, 1991.

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J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill. Sequential circuit veri cation using symbolic model checking. In Design Automation Conference, 1991.

No context found.

J. R. Burch, E. M. Clarke, K. L. McMillan, and D. L. Dill, \Sequential circuit veri cation using symbolic model checking," 28th Design Automation Conference, 1991.

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