See this document in CiteSeerX!

Relaxed Simulated Tempering for VLSI Floorplan Designs  (Make Corrections)  (10 citations)
Jason Cong, Tianming Kong, Dongmin Xu Computer Science Department University...



  Home/Search   Context   Related

 
View or download:
ucla.edu/~cong/pap...ac99_floorplan.pdf
Cached:  PDF   PS.gz  PS  Image  Update  Help

From:  ucla.edu/~cong/papers/ (more)
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: In the past two decades, the simulated annealing technique has been considered as a powerful approach to handle many NP-hard optimization problems in VLSI designs. Recently, a new Monte Carlo and optimization technique, named simulated tempering, was invented and has been successfully applied to many scientific problems, from random field Ising modeling to the traveling salesman problem. It is designed to overcome the drawback in simulated annealing when the problem has a rough energy... (Update)

Context of citations to this paper:   More

.... for each circuit is generated by running the simulated tempering (an improved Monte Carlo technique of simulated annealing) algorithm as in [24]. For each net, we first compute its best delay by optimal buffer insertion [21] and then randomly assign its delay budget to be ....

...and interconnect planning. Table 1 shows the quality of our physical planning engine compared to existing state of the art floorplanners [10][11] on a set of MCNC benchmarks. 4. EXPERIMENTAL RESULTS In this section, we report results to support the viability of the proposed...

Cited by:   More
Buffer Block Planning for Interconnect-Driven Floorplanning - Jason Cong Tianming   (Correct)
Physical Planning for On-Chip Multiprocessor Networks and.. - Ye, De Micheli (2003)   (Correct)
Decoupling Capacitance Allocation for Power Supply - Noise Suppression Shiyou   (Correct)

Similar documents (at the sentence level):
79.3%:   Relaxed Simulated Tempering for VLSI Floorplan Designs - Cong, Kong, Xu, Liang, Liu, .. (1999)   (Correct)

Active bibliography (related documents):   More   All
0.5:   Width of Floorplan - Where Every Module   (Correct)
0.3:   Fast Floorplanning For Effective Prediction And Construction - Ranjan Bazargan Sarrafzadeh (2001)   (Correct)
0.2:   Area Minimization for Hierarchical Floorplans - Pan (1996)   (Correct)

Similar documents based on text:
99.0:   Unknown -   (Correct)

Related documents from co-citation:   More   All
6:   Interconnect design for deep submicron ICs - Cong, He et al. - 1997
6:   Closed form solution to simultaneous buffer insertion/sizing and wire sizing (context) - Chu, Wong - 1997
6:   Challenges and opportunities for design innovations in nanometer technologies - Cong - 1997

BibTeX entry:   (Update)

@misc{ tianming-relaxed,
  author = "Jason Cong Tianming",
  title = "Relaxed Simulated Tempering for VLSI Floorplan Designs",
  url = "citeseer.ist.psu.edu/cong99relaxed.html" }
Citations (may not include all citations):
1527   Optimization by simulated annealing - Kirkpatrick, Gelatt et al. - 1983
266   Gibbs distributions and the Bayesian restoration of images (context) - Geman, Geman - 1984
69   Simulated tempering: a new Monte Carlo scheme (context) - Marinari, Parisi - 1992
42   Rectangle-packing-based module placement - Murata, Fujiyoshi et al. - 1995
34   Optimal orientation of cells in slicing floorplan designs (context) - Stockmeyer - 1983
19   Module placement on BSG-structure and IC layout applications (context) - Nakatake, Fujiyoshi et al. - 1996
17   Efficient floorplan optimization (context) - Otten - 1983
12   Floorplan design of VLSI circuits (context) - Wong, Liu - 1989
6   Dynamic weighting in Monte Carlo and optimization (context) - Wong, Liang - 1997
6   An optimal algorithm for floorplan area optimization (context) - Wang, Wong - 1990
4   Area minimization for general floorplans (context) - Pan, Liu - 1993
2   Thompson Annealing Markov chain Monte Carlo with application.. (context) - Geyer - 1995
2   Monte Carlo methods In New York : Wiley (context) - Kalos, Whitlock - 1986
2   Temperature schedules for simulated annealing (context) - Stander, Silverman - 1994
1   Simulated tempering procedure for spin-glass simulations (context) - Kerler, Rehberg - 1994
http://www.cbl.ncsu.edu/benchmarks/"



The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://cadlab.cs.ucla.edu/~cong/papers/):   More
Boolean Matching for Complex PLBs in LUT-based FPGAs with.. - Cong, Hwang (1998)   (Correct)
Improved Crosstalk Modeling for Noise Constrained.. - Jason Cong University   (Correct)
Challenges and Opportunities for Design Innovations in Nanometer.. - Cong (1997)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC