3.9 Debugging functions (1993) [1 citations — 0 self]
Abstract:
This paper reviews the development of the probabilistic RAM (pRAM) from its conception to the present day. One of the chief aims of this model of an artificial neuron has been to implement suitable learning rules in hardware. This work spans the development of single neuron models to an architecture for implementing large-scale pRAM networks and on to artificial neurons with temporal responses. pRAM development Four generations of pRAM hardware have so far been developed, three of which are in VLSI [1,2,3]. In 1988, the first hardware pRAMs were built as 2-input devices constructed (Fig. 1) using LSI logic parts. A small net, comprising two of these devices was shown to give results which agreed well with earlier theoretical analysis. The results of this net show the distinctive pulse-train output of such devices (Fig. 1). Tasks such as mutual inhibition or mutual excitation were successfully learned. The training was achieved by running the pRAM hardware for a single iteration on a PC interface card and the output of the pRAMs was then read. A reinforcement learning rule was applied in software on the PC and the updated weights were written back to the hardware before the next iteration was started. Following the success of this small-scale system the VLSI design of a 4-input pRAM was completed in early 1990. These devices still relied upon a host computer to perform the
