(Enter summary)
Abstract: Application-specific extensions to the computational capabilities of a processor provide an efficient mechanism to meet the
growing performance and power demands of embedded applications. Hardware, in the form of new function units (or coprocessors),
and the corresponding instructions are added to a baseline processor to meet the critical computational demands of a target
application. In this paper, the design of a system to automate the instruction set customization process is presented. A... (Update)
Cited by: More
Scalable Subgraph Mapping for Acyclic Computation.. - Clark, Hormati, Mahlke.. (2006)
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Active bibliography (related documents): More All
2.8: Processor Acceleration Through Automated Instruction Set.. - Clark, Zhong, Mahlke (2003)
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1.0: Automatically Generating Custom Instruction Set Extensions - Clark, Tang, Mahlke (2002)
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0.6: Exploring the Design Space of LUT-based Transparent.. - Yehia, Clark, Mahlke.. (2005)
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BibTeX entry: (Update)
N. Clark, H. Zhong, and S. Mahlke. Automated custom instruction generation for domain-specific processor acceleration. Trans. on Computers, 54(10):1258--1270, 2005. http://citeseer.ist.psu.edu/clark05automated.html More
@misc{ clark05automated,
author = "N. Clark and H. Zhong and S. Mahlke",
title = "Automated custom instruction generation for domain-specific processor acceleration",
text = "N. Clark, H. Zhong, and S. Mahlke. Automated custom instruction generation
for domain-specific processor acceleration. Trans. on Computers, 54(10):1258--1270,
2005.",
year = "2005",
url = "citeseer.ist.psu.edu/clark05automated.html" }
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