The Design and Veri cation of a Sorter Core
Download:
by Koen Claessen, Mary Sheeran, Satnam Singh
http://www.cs.chalmers.se/~ms/sorter_verification.pdf
Add To MetaCart
Abstract:
Abstract. The design and veri cation of a high speed sorter core is presented. We present several techniques and tools used to verify the functionality of the sorter. The sorter is a periodic sorter based on recursive butter y networks. Having a design language that is well-suited to describing these networks has helped us to explore the design space far more e ectively than is possible using conventional hardware description languages. 1
Citations
| 380 | Sorting networks and their applications – Batcher - 1968 |
| 58 | The periodic balanced sorting network – Dowd, Perl, et al. - 1989 |
| 17 | Sorting and Searching, vol. 3 of The Art of Computer Programming – Knuth - 1973 |
| 5 | A tutorial on Lava: A hardware description and veri cation system. Available from http://www.cs.chalmers.se/~koen/Lava – Claessen, Sheeran - 2000 |
| 2 | The study of butter ies – Jones, Sheeran - 1991 |
| 2 | Puzzling permutations – Sheeran - 1996 |
| 1 | A sequential sorting network analagous to the Batcher merge – eld, Williamson - 1991 |
| 1 | Lillieroth and Satnam Singh. Formal veri cation of FPGA cores – Johan - 1999 |
