Marcelo Cintra, Josep Torrellas  Home/Search
Context Related
Links: ACM | uiuc.edu/iacomapapers/learn02.pdf Cached: PS.gz PS PDF This document uses CoBlitz to cache paper downloads. If your firewall is blocking outgoing connections to port 3125, you can use these links to download local copies.
Image Update HelpPS.gz PS PDF From: uiuc.edu/papers (more) (Enter author homepages) |
Rate this article:      (best)Comment on this article |
Abstract: With speculative thread-level parallelization, codes that cannot be fully compiler-analyzed are aggressively executed in parallel. If the hardware detects a cross-thread dependence violation, it squashes offending threads and resumes execution. Unfortunately, frequent squashing cripples performance. (Update)
Context of citations to this paper: More
...hardware support in the coherence protocol to detect memory dependence violations. In recent work, Steffan et. al [21] and Cintra et. al [7] examine different methods of improving memory value communication in such a system. The load value prediction approach they describe,...
.... These were not used in the heap sort example, but will be discussed briefly here for completeness; more details can be found in [3][5][6] 8] 12] 14] 15] 17] The techniques comprise loop chunking, loop slicing, parallel reductions and explicit synchronization. Loop...
Cited by: More
Tolerating Dependences Between Large Speculative.. - Christopher Colohan.. (Correct)
Journal of Instruction-Level Parallelism 5 (2003) 1-21.. - The Role Of (Correct)
The Jrpm System for Dynamically Parallelizing Java Programs - Chen, Olukotun (2003) (Correct)
Active bibliography (related documents): More All
1.2: Architectural Support for Scalable Speculative.. - Cintra, Martinez.. (2000) (Correct)
1.2: Software Logging under Speculative Parallelization - Garzaran, Prvulovic.. (Correct)
0.4: The Role of Return Value Prediction in Exploiting Speculative .. - Shiwen Hu Ravi (2002) (Correct)
Similar documents based on text: More All
0.4: Removing Architectural Bottlenecks to the.. - Prvulovic.. (Correct)
0.3: Speculative Parallel Execution of Loops with.. - Zhang, Rauchwerger.. (1997) (Correct)
0.3: Speculative Locks for Concurrent Execution of Critical.. - Martinez, Torrellas (2001) (Correct)
Related documents from co-citation: More All
4: Improving Value Communication for Thread-Level Speculation - Steffan, Colohan et al. - 2002
3: A Scalable Approach to Thread-Level Speculation - Steffan, Colohan et al. - 2000
3: Compiler optimization of scalar value communication between speculative threads - Zhai, Colohan et al. - 2002
BibTeX entry: (Update)
M. Cintra and J. Torrellas. Eliminating squashes through learning cross-thread violations in speculative parallelization for multiprocessors. In HPCA, 2002. http://citeseer.ist.psu.edu/cintra02eliminating.html More
@misc{ cintra02eliminating,
author = "M. Cintra and J. Torrellas",
title = "Eliminating squashes through learning cross-thread violations in speculative
parallelization for multiprocessors",
text = "M. Cintra and J. Torrellas. Eliminating squashes through learning cross-thread
violations in speculative parallelization for multiprocessors. In HPCA,
2002.",
year = "2002",
url = "citeseer.ist.psu.edu/cintra02eliminating.html" }
Citations (may not include all citations):269 Multiscalar Processors - Sohi, Breach et al. - 1995
159 The LRPD Test: Speculative RunTime Parallelization of Loops .. - Rauchwerger, Padua - 1995
145 Exceeding the Dataflow Limit via Value Prediction - Lipasti, Shen - 1996 ACM DBLP
139 The Predictability of Data Values - Sazeides, Smith - 1997 ACM DBLP
116 Highly Accurate Data Value Prediction Using Hybrid Predictor.. - Wang, Franklin - 1997 ACM DBLP
110 Improving the Accuracy of Dynamic Branch Prediction Using Br.. (context) - Pan, So et al. - 1992 ACM DBLP
102 Dynamic Speculation and Synchronization of Data Dependences - Moshovos, Breach et al. - 1997 ACM DBLP
79 Removing Architectural Bottlenecks to the Scalability of Spe.. - Prvulovic, Garzaran et al. ACM DBLP
74 Speculative Versioning Cache - Gopal, Vijaykumar et al. - 1998 ACM DBLP
72 A Dynamic Multithreading Processor - Akkary, Driscoll - 1998 ACM DBLP
72 Data Speculation Support for a Chip Multiprocessor (context) - Hammond, Wiley et al. - 1998 ACM DBLP
64 Memory Dependence Prediction Using Store Sets - Chrysos, Emer - 1998 ACM DBLP
44 Hardware for Speculative Run-time Parallelization in Distrib.. - Zhang, Rauchwerger et al. - 1998 ACM DBLP
43 Advanced Program Restructuring for High-Performance Computer.. - Blume, Doallo et al. - 1996
38 Architectural Support for Scalable Speculative Parallelizati.. - Cintra, nez et al. - 2000 ACM DBLP
38 A Scalable Approach to Thread-Level Speculation - Steffan, Colohan et al. - 2000
30 Clustered Speculative Multithreaded Processors - Marcuello, alez - 1999 ACM DBLP
30 A Chip-Multiprocessor Architecture with Speculative Multithr.. - Krishnan, Torrellas - 1999 ACM DBLP
23 Speculation Techniques for Improving Load Related Instructio.. - Yoaz, Erez et al. - 1999
22 The Superthreaded Processor Architecture - Tsai, Huang et al. - 1999 ACM DBLP
21 Task Selection for a Multiscalar Processor - Vijaykumar, Sohi - 1998 ACM DBLP
20 MAJC: Microprocessor Architecture for Java Computing (context) - Tremblay - 1999
19 Value Prediction for Speculative Multithreaded Architectures - Marcuello, Tubella et al. - 1999 ACM DBLP
17 A Direct-Execution Framework for Fast and Accurate Simulatio.. - Krishnan, Torrellas - 1998
10 Improving Value Communication for Thread-Level Speculation - Steffan, Colohan et al. - 2002 ACM DBLP
9 Multiplex: Unifying Conventional and Speculative Thread-Leve.. - Ooi, Kim et al. - 2001 DBLP
9 SPEComp: A New Benchmark Suite for Measuring Parallel Comput.. - Aslot, Domeika et al. - 2001 DBLP
6 Limits on Speculative Module-Level Parallelism in Imperative.. - Warg, om - 2001 ACM DBLP
5 In Search of Speculative Threadlevel Parallelism (context) - Oplinger, Heine et al. - 1999
2 A Front End for Efficient Simulation of Shared-Memory Multip.. (context) - Veenstra, Fowler - 1994
2 Techniques for Run-Time Parallelization of Loops (context) - Gupta, Nim - 1998
1 A Software Approach to ThreadLevel Data Dependence Speculati.. (context) - Rundberg, om - 2000
Documents on the same site (http://iacoma.cs.uiuc.edu/papers.html): More
Comprehensive Hardware and Software Support for Operating.. - Xia, Torrellas (1999) (Correct)
Software Trace Cache - Ramírez, Larriba-Pey.. (1999) (Correct)
An Efficient Algorithm for the Run-time Parallelization of .. - Chen, Torrellas, Yew (1994) (Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC