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Abstract: Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs... (Update)
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BibTeX entry: (Update)
M. Cintra, J. F. Martnez, and J. Torrellas. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors. In Proceedings of ISCA 27, June 2000. http://citeseer.ist.psu.edu/cintra00architectural.html More
@inproceedings{ cintra:isca00,
author = "Marcelo Cintra and Jos{\'e} F. Mart{\'\i}nez and Josep Torrellas",
title = "Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors",
pages = "13--24",
booktitle = "International Symposium on Computer Architecture (ISCA)",
address = "Vancouver, Canada",
month = jun,
year = "2000",
url = "citeseer.ist.psu.edu/cintra00architectural.html" }
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