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Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors (2000)  (Make Corrections)  (38 citations)
Marcelo Cintra, Jose F. Martinez, Josep Torrellas
International Symposium on Computer Architecture (ISCA)



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Abstract: Speculative parallelization aggressively executes in parallel codes that cannot be fully parallelized by the compiler. Past proposals of hardware schemes have mostly focused on single-chip multiprocessors (CMPs), whose effectiveness is necessarily limited by their small size. Very few schemes have attempted this technique in the context of scalable shared-memory systems. In this paper, we present and evaluate a new hardware scheme for scalable speculative parallelization. This design needs... (Update)

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28:   A Scalable Approach to Thread-Level Speculation - Steffan, Colohan et al. - 2000
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BibTeX entry:   (Update)

M. Cintra, J. F. Martnez, and J. Torrellas. Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors. In Proceedings of ISCA 27, June 2000. http://citeseer.ist.psu.edu/cintra00architectural.html   More

@inproceedings{ cintra:isca00,
    author = "Marcelo Cintra and Jos{\'e} F. Mart{\'\i}nez and Josep Torrellas",
    title = "Architectural Support for Scalable Speculative Parallelization in Shared-Memory Multiprocessors",
    pages = "13--24",
    booktitle = "International Symposium on Computer Architecture (ISCA)",
    address = "Vancouver, Canada",
    month = jun,
    year = "2000",
    url = "citeseer.ist.psu.edu/cintra00architectural.html" }
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357   The Directory-Based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990  ACM   DBLP
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197   Maximizing Multiprocessor Performance with the SUIF Compiler - Hall, Anderson et al. - 1996  DBLP
159   The LRPD Test: Speculative RunTime Parallelization of Loops .. - Rauchwerger, Padua - 1995
74   Speculative Versioning Cache - Gopal, Vijaykumar et al. - 1998  ACM   DBLP
72   A Dynamic Multithreading Processor - Akkary, Driscoll - 1998  ACM   DBLP
72   Data Speculation Support for a Chip Multiprocessor (context) - Hammond, Wiley et al. - 1998  ACM   DBLP
67   ARB: A Hardware Mechanism for Dynamic Reordering of Memory R.. - Franklin, Sohi - 1996  DBLP
44   Hardware for Speculative Run-Time Parallelization in Distrib.. - Zhang, Rauchwerger et al. - 1998  ACM   DBLP
43   Advanced Program Restructuring for High-Performance Computer.. - Blume, Doallo et al. - 1996
42   Improving the Performance of Runtime Parallelization - Leung, Zahorjan - 1993  ACM   DBLP
38   A Scalable Approach to Thread-Level Speculation - Steffan, Colohan et al. - 2000  ACM   DBLP
30   Clustered Speculative Multithreaded Processors - Marcuello, Gonzalez - 1999  ACM   DBLP
30   A Chip-Multiprocessor Architecture with Speculative Multithr.. - Krishnan, Torrellas - 1999  ACM   DBLP
26   An Architecture for Mostly Functional Languages (context) - Knight - 1986  ACM   DBLP
20   MAJC: Microprocessor Architecture for Java Computing (context) - Tremblay - 1999
19   Architectural Support for ThreadLevel Data Speculation - Steffan, Mowry - 1997
17   A Direct-Execution Framework for Fast and Accurate Simulatio.. - Krishnan, Torrellas - 1998
12   Hardware for Speculative Parallelization of Partially-Parall.. - Zhang, Rauchwerger et al. - 1999
2   Hardware for Speculative Parallelization in DSM Multiprocess.. (context) - Zhang - 1999
2   Techniques for Run-Time Parallelization of Loops (context) - Gupta, Nim - 1998
2   A Front End for Efficient Simulation of Shared-Memory Multip.. (context) - Veenstra, Fowler - 1994



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