Synchronous transfer architecture (STA (2004) [13 citations — 8 self]

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by Gordon Cichon, P. Robelly, H. Seidel, M. Bronzel, Gerhard Fettweis

in Lecture Notes on Computer Science

http://www.ifn.et.tu-dresden.de/MNS/veroeffentlichungen/2004/Cichon_G_SAMOS_04.pdf

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@INPROCEEDINGS{Cichon04synchronoustransfer,
    author = {Gordon Cichon and P. Robelly and H. Seidel and M. Bronzel and Gerhard Fettweis},
    title = {Synchronous transfer architecture (STA},
    booktitle = {in Lecture Notes on Computer Science},
    year = {2004},
    pages = {126--130},
    publisher = {Springer-Verlag}
}

Abstract:

Abstract. This paper presents a novel micro-architecture for high-performance and low-power DSPs. The underlying Synchronous Transfer Architecture (STA) fills the gap between SIMD-DSPs and coarse-grain reconfigurable hardware. STA processors are modeled using a common machine description suitable for both compiler and core generator. The core generator is able to generate models in Lisa, System-C, and VHDL. A special emphasis is placed on the good synthesis of the generated VHDL model. 1

Citations

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59	Microprocessor Architectures from VLIW to TTA – Corporaal - 1997
26	Hardware/software instruction set configurability for system on-chip processors – Wang, Killian, et al. - 2001
20	Advanced Compiler Design and Implementation – Muchnik - 1997
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1	Cambon. Metrics for digital signal processing architectures characterization: Remancence and scalability – Benoit, Sassatelli, et al. - 2003
1	MOUSE online core generator. http://www. radionetworkprocessor.com/gencore.php – Cichon
1	An automatically generated core-based implementation of an OFDM communication system – Seidel, Matúˇs, et al. - 2004
1	The VelociTI TM architecture of the TMS320C6xxx – Truong - 1997
1	machine description language and generic machine model for HW/SW co-design – LISA - 1996

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