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by Gordon Cichon, P. Robelly, H. Seidel, M. Bronzel, Gerhard Fettweis
In Proc. of Fourth International Conference on Parallel Computing in Electrical Engineering (PARELEC’04
http://media.radionetworkprocessor.com/Parelec-2004.pdf
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Abstract:
This paper presents an adaptation of the list scheduling algorithm to generate code for processors of the Synchronous Transfer Architecture (STA) by applying techniques known from RISC and TTA. The proposed scheduling approach is based on informed, deterministic algorithms that can be implemented run-time efficiently. Although the presented compiler prototype does not generate optimized code, it provides a proof-of-concept of the feasibility of the proposed compiler architecture. 1
Citations
|
3148
|
Computer Architecture: A Quantitative Approach
– Hennessy, Patterson
- 1996
|
|
401
|
Supercompilers for Parallel and Vector Computers
– Zima, Chapman
- 1991
|
|
112
|
Optimizing Compilers for Modern Architectures
– Allen, Kennedy
- 2002
|
|
63
|
The IBM research parallel processor prototype (RP3): Introduction and architecture
– PFISTER, BRANTLEY, et al.
- 1985
|
|
59
|
Microprocessor Architectures from VLIW to TTA
– Corporaal
- 1997
|
|
55
|
Retargetable Code Generation for Digital Signal Processors
– Leupers
- 1997
|
|
26
|
Hardware/software instruction set configurability for system on-chip processors
– Wang, Killian, et al.
- 2001
|
|
20
|
Advanced Compiler Design and Implementation
– Muchnik
- 1997
|
|
13
|
Synchronous transfer architecture (STA
– Cichon, Robelly, et al.
- 2004
|
|
11
|
Dynamic codewidth reduction for VLIW instruction set architectures in digital signal processors
– WEISS, FETTWEIS
- 1996
|
|
10
|
Register file port requirements of transport triggered architectures
– Hoogerbrugge, Corporaal
- 1994
|
|
5
|
GNU Compiler Collection Internals. http://gcc.gnu.org/onlinedocs/gccint/, Free Software Foundation
– Stallman
- 2003
|
|
1
|
Beiträge zur Optimierten Code-Erzeugung
– Römer
- 2004
|