JaeWoong Chung, Hassan Chafi, Chi Cao Minh, Austen McDonald, Brian D....  Home/Search
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Abstract: Transactional memory (TM) provides an easy-to-use and high-performance parallel programming model for the upcoming chip-multiprocessor systems. Several researchers have proposed alternative hardware and software TM implementations. However, the lack of transaction-based programs makes it difficult to understand the merits of each proposal and to tune future TM implementations to the common case behavior of real application. (Update)
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BibTeX entry: (Update)
J. Chung et al. The Common Case Transactional Behavior of Multithreaded Programs. In Proceedings of the 12th Intl. Conference on High Performance Computer Architecture, Feb. 2006. http://citeseer.ist.psu.edu/chung06common.html More
@misc{ chung06common,
author = "J. Chung",
title = "The Common Case Transactional Behavior of Multithreaded Programs",
text = "J. Chung et al. The Common Case Transactional Behavior of Multithreaded
Programs. In Proceedings of the 12th Intl. Conference on High Performance
Computer Architecture, Feb. 2006.",
year = "2006",
url = "citeseer.ist.psu.edu/chung06common.html" }
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http://httpd.apache.org/
http://www.mpeg.org/MSSG/
http://www.spec.org/omp/
http://www.nas.nasa.gov/Software/NPB/
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Transactional Execution of Java Programs - Brian Carlstrom Jaewoong (2005) (Correct)
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Characterization of TCC on Chip-Multiprocessors - Austen Mcdonald Jaewoong (2005) (Correct)
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