Amit Chowdhary, Sudhakar Kale, Phani Saripella, Naresh Sehgal  Home/Search
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Abstract: In majority of high-performance custom IC designs, designers take advantage of the high degree of regularity present in circuits to generate e#cientlayouts in terms area and performance as well as to reduce the design e#ort. In this paper, we explain how regularity manifests itself at functional, structural and topological levels. Using these notions, we present a general and comprehensive approach to extract functional regularity for datapath circuits from their high-level or gate-level... (Update)
Context of citations to this paper: More
.... of regularity; hence regularity extraction reduces the complexity of the program as well as increasing the quality of the result [10,11]. System level partitioning is yet another use of regularity extraction [12] Furthermore, proper use of templates can lead to low power...
.... including, but not limited to, scheduling during logic synthesis [1] system level partitioning [2] and FPGA mapping and placement [3]. We aim to build a general profiling technique for simultaneous template generation and matching, which is applicable to any task that...
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BibTeX entry: (Update)
A. Chowdhary, S. Kale, P. Saripella, N. Sehgal, and R. Gupta. "A General Approach for Regularity Extraction in Datapath Circuits". In IEEE International Conference on ComputerAided Design, pages 332--339, 1998. http://citeseer.ist.psu.edu/chowdhary98general.html More
@inproceedings{ chowdhary98general,
author = "Amit Chowdhary and Sudhakar Kale and Phani Saripella and Naresh Sehgal and Rajesh Gupta",
title = "A general approach for regularity extraction in datapath circuits",
booktitle = "{ICCAD}",
pages = "332-339",
year = "1998",
url = "citeseer.ist.psu.edu/chowdhary98general.html" }
Citations (may not include all citations):2 on Physical Design (context) - Symp - 1997
1 on AdvancedResearch in VLSI (context) - Conf - 1997
The graph only includes citing articles where the year of publication is known.
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