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Abstract: In this paper, we propose a new multicomputer node architecture, the DI-multicomputer which uses packet routing on a uniform point-to-point interconnect for both local memory access and internode communication. This is achieved by integrating a router onto each processor chip and eliminating the memory bus interface. Since communication resources such as pins and wires are allocated dynamically via packet routing, the DI-multicomputer is able to maximize the available communication resources,... (Update)
Context of citations to this paper: More
.... critical and getting increasingly so [17] and flexible interconnects can be used to replace static wires at competitive performance [6, 9, 20]. Our approach presents an improvement over co processing by preserving machine usability through software and over traditional...
.... and getting increasingly so [19] and (2) flexible interconnects can be used to replace static wires at competitive performance [20, 21, 22, 23]. The key elements of the MORPH architecture include processing elements and memory elements embedded in a scalable...
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BibTeX entry: (Update)
CHOI, L., AND CHIEN, A. A. The design and performance evaluation of the DI-multicomputer. J. Parallel and Distributed Comput, 36:119--143, 1996. http://citeseer.ist.psu.edu/choi96design.html More
@article{ choi96design,
author = "Lynn Choi and Andrew A. Chien",
title = "The design and performance evaluation of the {DI}-multicomputer",
journal = "Journal of Parallel and Distributed Computing",
volume = "36",
number = "2",
pages = "119--143",
year = "1996",
url = "citeseer.ist.psu.edu/choi96design.html" }
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191 The MIT Alewife Machine: A Large-Scale Distributed-Memory Mu.. - Agarwal - 1991
187 Ethernet: Distributed packet-switching for local computer ne.. (context) - Metcalfe, Boggs - 1976
154 Planar-adaptive routing: Low-cost adaptive networks for mult.. - Chien, Kim - 1992
138 The turn model for adaptive routing - Ni, Glass - 1992
108 Paragon XP/S Product Overview (context) - Corporation - 1991
97 A cost and speed model for k-ary n-cube wormhole routers - Chien - 1993
93 IEEE Transactions on Parallel and Distributed Systems (context) - Dally - 1992
85 CM-5 Technical Summary (context) - Corporation, Massachusetts - 1991
75 Machine: A fine-grain concurrent computer (context) - Dally, Chien et al. - 1989
72 Alpha Architecture Handbook (context) - Corporation - 1992
70 The scalable coherent interface and related standards projec.. (context) - Gustavson - 1992
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58 Adaptive deadlock and livelock free routing with all minimal.. - Berman, Gravano et al. - 1992
39 Exploiting heterogeneous parallelism on a multithreaded mult.. (context) - Alverson, Alverson et al. - 1992
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32 A protocol for packet network interconnection (context) - Cerf, Kahn - 1974
24 Express cubes: Improving the performance of k-ary n-cube int.. (context) - Dally - 1991
23 The message-driven processor (context) - Dally, Fiske et al. - 1992
22 Design of a self-timed vlsi multicomputer communication cont.. (context) - Dally, Song - 1987
21 Life Span Strategy - A Compiler-Based Approach to Cache Cohe.. (context) - Cheong - 1992
20 A Compiler-Directed Cache Coherence Scheme with Improved Int.. - Choi, Yew - 1994
15 The cost of adaptivity and virtual lanes in a wormhole route.. - Aoyama - 1994
12 The Directory-Based Cache Coherence Protocol for the DASH Co.. (context) - Laudon, Gharachorloo et al. - 1990
11 Let's route packets instead of wires (context) - Seitz - 1990
8 Rambus architectural overview (context) - Corporation - 1992
8 Integrating networks and memory hierarchies in a multicomput.. - Choi, Chien - 1994
7 iWarp: a 100-MOPS LIW microprocessor for multicomputers (context) - Peterson, Sutton et al. - 1991
6 AP1000 architecture and performance of LU decomposition (context) - Horie - 1991
5 XP Microprocessor Data Book (context) - Corporation - 1991
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2 Electrical design of a high speed computer packaging system (context) - Davidson - 1983
1 Analysis of high-speed bus lines in printed circuit boards (context) - Matsui, Satoh et al. - 1989
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