(Enter summary)
Abstract: This paper illustrates a formal technique for describing
the timing properties and resource constraints
of pipelined superscalar processor instructions at high
level. Superscalar processors can issue and execute
multiple instructions simultaneously. The degree of
parallelism depends on the multiplicity of hardware
functional units as well as data dependencies among
instructions. Thus, the timing properties of a superscalar
program is difficult to analyze and predict.
We describe how to model... (Update)
Context of citations to this paper: More
...guaranteed, or enormous cost is needed. Due to these limitations, analytical approaches are becoming more popular [4, 5, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16]. Many of these analytical studies, however, consider a simple machine model, thus largely ignoring the timing effects...
...approaches, analytical approaches are becoming more popular. There have been several recent studies about this issue [4, 8, 9, 18, 19, 20, 22, 23, 24, 27, 28]. In many of these studies, the assumed machine model is a simple non pipelined processor without cache memory [18, 22,...
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BibTeX entry: (Update)
J.-Y. Choi, I. Lee, and I. Kang, "Timing Analysis of Superscalar Processor Programs Using ACSR," in Proceedings of the 11th Workshop on Real-Time Operating Systems and Software, pp. 63--67, May 1994. http://citeseer.ist.psu.edu/choi94timing.html More
@misc{ choi94timing,
author = "J. Choi and I. Lee and I. Kang",
title = "Timing Analysis of Superscalar Processor Programs Using ACSR",
text = "J.-Y. Choi, I. Lee, and I. Kang, Timing Analysis of Superscalar Processor
Programs Using ACSR, in Proceedings of the 11th Workshop on Real-Time Operating
Systems and Software, pp. 63--67, May 1994.",
year = "1994",
url = "citeseer.ist.psu.edu/choi94timing.html" }
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