by Hsiao-feng Steven Chen, D. T. Lee
http://web.eecs.nwu.edu/~dtlee/IEEEtcad_crossing.ps.Z
Add To MetaCart
Abstract:
In this paper we consider a problem related to global routing post-optimization: the crossing minimization problem (CMP). Given a global routing representation, the CMP is to minimize redundant crossings between every pair of nets. In particular, there are two kinds of CMP: constrained CMP (CCMP) and unconstrained CMP (UCMP). These problems have been studied previously in [Groe89], where an O(m 2 n) algorithm was proposed for CCMP, and in [MS95], where an (mn 2
Citations
|
1541
|
Computational Geometry: An Introduction
– Preparata, Shamos
- 1985
|
|
364
|
Combinatorical algorithms for integrated circuit layout. Applicable Theory
– Lengauer
- 1990
|
|
73
|
Fundamentals of Data Structures
– Horowitz, Sahni
- 1976
|
|
27
|
Algorithms for routing and testing routability of planar VLSI layouts
– Leiserson, Maley
- 1985
|
|
26
|
A global router using an efficient approximate multicommodity multiterminal flow algorithm
– Carden, Cheng
- 1991
|
|
24
|
Global routing based on Steiner min-max trees
– Chiang, Sarrafzadeh, et al.
- 1990
|
|
23
|
Rubber Band Routing and Dynamic Data Representation
– Dai, Kong, et al.
- 1990
|
|
19
|
Topological Routing in SURF: Generating a Rubber-Band Sketch
– Dai, Dayan, et al.
- 1991
|
|
18
|
Pin assignment with global routing for general cell designs
– Cong
- 1991
|
|
11
|
The Crossing Distribution Problem
– Marek-Sadowska, Sarrafzadeh
- 1995
|
|
9
|
Optimal Channel Pin Assignment
– Cai, Wong
- 1991
|
|
9
|
Global Routing for Gate Arrays
– Li, Marek-Sadowska
- 1984
|
|
7
|
Routing region definition and ordering scheme for building-block layout
– Dai, Asano, et al.
- 1985
|
|
7
|
Cross Point Assignment with Global Rerouting for General-Architecture Designs
– Kao, Parng
- 1995
|
|
5
|
Layout Design and Verification
– Ohtsuki
- 1986
|
|
4
|
A faster algorithm for rubber-band equivalent transformation for planar VLSI layouts
– Chen, Lee
- 1996
|
|
4
|
On global wire ordering for macro-cell routing
– GROENVELD
- 1989
|
|
3
|
A Dynamic and efficient Representation of Building-Block Layout
– Dai, Sato, et al.
- 1987
|
|
2
|
Topological Optimization for VLSI Layout Design
– Chen
- 1997
|
|
1
|
BBL: A Building Block Layout System for Custom Chip Design
– Chen, Hsu, et al.
- 1983
|
