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Abstract: In this paper we present a straightforward technique for compressing the instruction stream for programs that overcomes some of the limitations of earlier proposals. After code generation, the instruction stream is analysed for frequently used sequences of instructions from within the program's basic blocks. These patterns of multiple instructions are then mapped into single byte opcodes. This constitutes a compression of multiple, multi-byte operations onto a single byte. When compressed... (Update)
Context of citations to this paper: More
...sequences of any length. 3 Compression Method 3. 1 Algorithm Our compression method is based on the technique introduced in [Bird96][Chen97a]. A dictionary compression algorithm is applied after the compiler has generated the program. We take advantage of SDTS and find...
...time of commodity DRAM. Reducing program size is one way to reduce instruction cache misses and provide higher instruction bandwidth [Chen97a]. Our contribution Both low cost embedded systems and high performance microprocessors can benefit from small program sizes. This...
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BibTeX entry: (Update)
I. Chen, P. Bird, and T. Mudge, The Impact of Instruction Compression on I-cache Performance, CSE-TR-330-97, EECS Department, University of Michigan, 1997. http://citeseer.ist.psu.edu/chen97impact.html More
@techreport{ chen97impact,
author = "I-Cheng K. Chen and Peter L. Bird and Trevor Mudge",
title = "The Impact of Instruction Compression on {I}-cache Performance",
number = "CSE-TR-330-97",
month = "13",
year = "1997",
url = "citeseer.ist.psu.edu/chen97impact.html" }
Citations (may not include all citations):866 Techniques and Tools (context) - Aho, Sethi et al. - 1986
183 Trace Cache: a Low Latency Approach to High Bandwidth Instru.. - Rotenberg, Bennett et al. - 1996
173 Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1985
65 Studies of Windows NT performance using dynamic execution tr.. - Perl, Sites - 1996
57 Executing Compressed Programs on an Embedded RISC Architectu.. (context) - Wolfe, Chanin - 1992
43 ATOM: A flexible interface for building high performance pro.. (context) - Eustace, Srivastava - 1995
9 Technical Manual (context) - CPU' - 1995
6 An Instruction Stream Compression Technique - Bird, Mudge - 1996
2 Trap-Driven Memory Simulation - Uhlig - 1995
Documents on the same site (http://www.eecs.umich.edu/~tnm/compress/compress-pubs.html): More
Improving Code Density Using Compression Techniques - Lefurgy, Bird, Chen, Mudge (1997) (Correct)
An Instruction Stream Compression Technique - Bird, Mudge (1996) (Correct)
Smart Register Files for High-Performance Microprocessors - Postiff, Mudge (1999) (Correct)
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