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Abstract: Non-blocking caches and prefetching caches are two techniques for hiding memory latency by exploiting the overlap of processor computations with data accesses. A non-blocking cache allows execution to proceed concurrently with cache misses as long as dependency constraints are observed, thus exploiting post-miss operations. A prefetching cache generates prefetch requests to bring data in the cache before it is actually needed, thus allowing overlap with pre-miss computations. In this paper, we... (Update)
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BibTeX entry: (Update)
T. Chen and J. Baer, "Reducing memory latency via non-blocking and prefetching caches," In Proceedings of the 5th Int. Conf. Architectural Support for Programming Languages and Operating Systems, pp. 51-61, Oct. 1992. http://citeseer.ist.psu.edu/chen92reducing.html More
@inproceedings{ chen92reducing,
author = "Tien-Fu Chen and Jean-Loup Baer",
title = "Reducing memory latency via non-blocking and prefetching caches",
booktitle = "Proceedings of the 5th International Conference on Architectural Support for Programming Languages and Operating System ({ASPLOS})",
journal = "SIGPLAN Notices",
volume = "27",
number = "9",
publisher = "ACM Press",
address = "New York, NY",
isbn = "0-89791-534-8",
pages = "51--61",
year = "1992",
url = "citeseer.ist.psu.edu/chen92reducing.html" }
Citations (may not include all citations):1575 Computer Architecture: A Quantitative Approach (context) - Hennessy, Patterson - 1990
443 Improving direct-mapped cache performance by the addition of.. - Jouppi - 1990
249 Tolerating latency through software-controlled prefetching i.. - Mowry, Gupta - 1991
234 Cache memories (context) - Smith - 1982
185 Branch prediction strategies and branch target buffer design (context) - Lee, Smith - 1984
137 Lockup-free instruction fetch/prefetch cache organization (context) - Kroft - 1981
122 An effective on-chip preloading scheme to reduce data access.. (context) - Baer, Chen - 1991
121 An architecture for software-controlled data prefetching (context) - Klaiber, Levy - 1991
112 The priority-based coloring approach to register allocation (context) - Chow, Hennessy - 1990
107 Software methods for improvement of cache performance on sup.. (context) - Porterfield - 1989
93 High-bandwidth data memory systems for superscalar processor (context) - Sohi, Franklin - 1991
92 Performance evaluation of memory consistency models for shar.. - Gharachorloo, Gupta et al. - 1991
83 Compiler-directed data prefetching in multiprocessor with me.. - Gornish, Granston et al. - 1990
77 Efficient instruction scheduling for a pipelined architectur.. (context) - Gibbons, Muchnick - 1986
42 Hiding memory latency using dynamic scheduling in shared-mem.. (context) - Gharachorloo, Gupta et al. - 1992
33 Circular scheduling: a new technique to perform software pip.. (context) - Jain - 1991
11 Writes caches as an alternative to write buffers (context) - Bray, Flynn - 1991
9 A brief survey of papers on scheduling for pipelined process.. (context) - Krishnamurthy - 1990
4 Multi-level cache hierarchies: Organizations (context) - Baer, Wang - 1989
2 The Art of Computer System Performance Anaylsis (context) - Jain - 1991
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