CiteSeer.IST HomeCheck: The following citations are predicted to all refer to the same paper. Details
D. M. Russinoff. Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits. Technical Report 99, Computational Logic, Inc., Austin, Texas, May, 1994. URL http://www.cli.com/.
D. M. Russinoff. Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits. Technical Report 99, Computational Logic, Inc., Austin, Texas, May, 1994.
Russinoff, D., Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits, forthcoming technical report, Computational Logic, Inc.
Russinoff, D., Specification and Verification of Gate-Level VHDL Models of Synchronous and Asynchronous Circuits, forthcoming technical report, Computational Logic, Inc.