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Abstract: Traditionally, VLSI architects and designers have acknowledged the area, performance, and effort tradeoffs between cell-based and full-custom implementations of the same datapath function. However, few attempts have been made to characterize these tradeoffs in the context of contemporary fabrication processes and area place and route tools. More importantly, few attempts have been made to determine how to enable cell-based implementations to approach the density and speed of full-custom... (Update)
Context of citations to this paper: More
...generating all of the views needed to support the standard cell tools, is quite low (0. 5 4 person days depending on complexity) [1][6] and that a very small number of cells (10 20) is sufficient to realize most datapaths. Moreover these cells are reusable. They really...
.... resulting design, by reducing the number of logic levels for implementing complex logic functions and reducing the area taken up by logic[5]. 5. FLOORPLANNING, PLACEMENT, AND ROUTING Wire delays associated with global wires between physical modules can be a dominant portion...
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BibTeX entry: (Update)
CHANG, ANDREW, VLSI Datapath Choices: Cell-Based Versus FullCustom, SM Thesis, Massachusetts Institute of Technology, February 1998. http://citeseer.ist.psu.edu/chang98vlsi.html More
@misc{ andrew98vlsi,
author = "C. ANDREW",
title = "VLSI Datapath Choices: Cell-Based Versus FullCustom",
text = "CHANG, ANDREW, VLSI Datapath Choices: Cell-Based Versus FullCustom, SM
Thesis, Massachusetts Institute of Technology, February 1998.",
year = "1998",
url = "citeseer.ist.psu.edu/chang98vlsi.html" }
Citations (may not include all citations):221 Introduction to VLSI Systems (context) - Mead, Conway - 1980 ACM
159 Principles of CMOS VLSI Design: A Systems Perspective (context) - Weste, Eshraghian - 1993
71 An Area Model for On-Chip Memories and its Application (context) - Mulder, Quach et al. - 1991
58 Digital Systems Engineering (context) - Dally, Poulton - 1998 ACM
56 A Case for Intelligent RAM: IRAM - Patterson, Anderson et al. - 1997
56 Machine Multicomputer (context) - Fillo, Keckler et al. - 1994
33 Architecture of the Pentium Microprocessor (context) - Alpert, Avnon - 1993 ACM
25 Performance Features of the PA7100 Microprocessor (context) - Asprey, Averill et al. - 1993 ACM
23 The Message Driven Processor (context) - Dally, Fiske et al. - 1992 ACM
14 A Comparison of CMOS Circuit Techniques: Differential Cascod.. (context) - Chu, Pulfrey - 1987
9 Ported CMOS Register File (context) - Jolly, -ns - 1991
8 The PowerPC 601 Microprocessor (context) - Becker, Allen et al. - 1993
7 BiCMOS processor with Dynamic Execution (context) - Colwell, Steck - 1995
6 A Module Area Estimator for VLSI Layout (context) - Chen, Bushnell - 1988 ACM DBLP
6 The MIT Multi-ALU Processor (context) - Keckler, Chang et al. - 1997
6 Microprocessor Report (context) - Gwennap - 1993
6 VIPER: A VLIW Integer Microprocessor - Gray, Naylor et al. - 1993
4 PPC 604 Powers Past Pentium (context) - Gwennap - 1994
4 TI Introduces Four Processor DSP Chip (context) - Feigel - 1994
4 Cell based Performance Optimization of Combinational Circuit.. (context) - Hinsberger, Kolla - 1990 ACM
3 Formal Sizing Rules of CMOS Circuits (context) - Auvergne, Azemard et al. - 1991 ACM
3 Microprocessor Report (context) - Slater, MIPS et al. - 1992
3 Evaluating Layout Area Tradeoffs for High Level Applications (context) - Kurdahi, Ramachandran - 1993
3 Quad-Issue CMOS Microprocessor (context) - Bowhil, MHz - 1995
3 Schematic Specification of Datapath Layout (context) - Curry - 1989
3 MHz CMOS Microprocessor with Multi-MediaTechnology (context) - Choudhury, Miller - 1997
3 Design Methodologie PALC Microprocessor (context) - Weir, Methodologies et al. - 1995
2 Optimization for Automatic Cell Assembly (context) - Dutt, Lakhani - 1988
2 Implementation of the PowerPC 601 microprocessor (context) - Brodnax, Billings et al. - 1994 ACM
2 in Review: The Top RISC Processors (context) - Gwennap - 1992
2 TFP Designed for Tremendous Floating Point (context) - Gwennap - 1993
2 A Sub-Nanosecond (context) - Naffziger
2 PA-7200 Enables Inexpensive MP Systems (context) - Gwennap - 1994
2 Microprocessors Lead the Way to (context) - Gwennap - 1995
2 Template Style Considerations for Sea-of-Gates Layout Genera.. (context) - Adams, Sequin - 1989 ACM DBLP
2 Large Standard Cell Libraries and Their Impact on Layout Are.. (context) - Guan, Sechen - 1996
1 bit 68000 microprocessor camps on 32-bit frontier (context) - Hartman - 1981
1 MHz BiCMOS Superscalar Microprocessor (context) - Cohen, Ballard et al. - 1997
1 Benchmarks for Cell Synthesis (context) - Hill, Preas - 1990 ACM DBLP
1 Quad-Issue CMOS RISC Microprocessor (context) - Gronowski, MHz - 1996
1 SuperSPARC (context) - Slater - 1991
1 Design Techniques for High-Speed Datapaths (context) - Irrissou - 1993 ACM
1 Design and implementation of the integer unit datapath of th.. - Gupta - 1996
1 microcomputer bridges the gap between 8- and 16-bit designs (context) - Katz, Morse et al. - 1981
1 MHz High-Speed Adder (context) - Srivastava
1 Automatic Layout Synthesis for High Performance Full Custom .. (context) - Kim - 1995
1 mm Processor Chips (context) - Klein, Koetzle et al. - 1987
1 A Dynamic Programming Approach to the Power Supply Net Sizin.. (context) - Kolla - 1990 ACM
1 Stanford University (context) - Dally - 1995 ACM
1 Communication-Oriented Architecure (context) - Dally - 1998
1 Barring it all to Software: Raw Machines (context) - Waingold, Taylor et al. - 1997
1 Machine Architecture v (context) - Dally, Keckler et al.
1 Alpha Hits Low End with Digital's (context) - Gwennap - 1993
1 The Reliable Router: An Architecture for Fault Tolerant Inte.. - Dennison - 1996
1 die photos (context) - Semiconductor, Alpha et al.
1 LSI processor mirrors high-performance minicomputer (context) - Druke, Gusowski et al. - 1981
1 IC Manufacturing Drives CPU Performance (context) - Gwennap - 1993
1 CPU Vendors Deploy Half-Micro Processes (context) - Gwennap - 1994
1 Motorola Introduces Heir to 68000 Line (context) - Feigel - 1994
1 Integrated PA-7300LC Powers HP Midrange (context) - Gwennap - 1995
1 System on a Chip (context) - Meyer
1 A High Density Datapath Compiler Mixing Random Logic with Op.. (context) - Ammar, Greiner - 1993
1 A Study of the Use of Local Interconnect in CMOS Leaf Cell D.. (context) - Bachelu, Lefebvre - 1993
1 Web Page: CPU Info Center - Microprocessor Info (context) - Burd
1 Two versions of 16-bit chip span microprocessor (context) - Shima - 1981
1 Premier as iXP (context) - Generation, XP et al. - 1991
1 Pseudo Pin Assignment for Single-Layer Over-the-Cell Routing (context) - Chen - 1990
1 VLSI Chip Design Productivity (context) - Fey - 1985
1 Studies in LSI Techology Economics II: A Comparison of Produ.. (context) - Fey, Parakevopoulos - 1986
1 Studies in LSI Techology Economics II: Models for Gate Array.. (context) - Fey, Parakevopoulos - 1989
1 bit RISC microprocessor (context) - Bishop, Campion et al. - 1996
1 Performance Driven Placement and Routing Algorithms (context) - Gao - 1994 ACM
1 Nautile: A Safe Environment for Silicon Compilation (context) - Bondono, Jerraya et al. - 1990
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