Pohua P. Chang, Scott A. Mahlke, William Y. Chen, Nancy J. Warter, Wen-mei W. Hwu  Home/Search
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Abstract: The performance of multiple-instruction-issue processors can be severely limited by the compiler's ability to generate efficient code for concurrent hardware. In the IMPACT project, we have developed IMPACT-I, a highly optimizing C compiler to exploit instruction level concurrency. The optimization capabilities of the IMPACT-I C compiler are summarized in this paper. Using the IMPACT-I C compiler, we ran experiments to analyze the performance of multiple-instruction-issue processors executing... (Update)
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41: Trace Scheduling: A Technique for Global Microcode Compaction (context) - Fisher - 1981
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BibTeX entry: (Update)
P. P. Chang, S. A. Mahlke, W. Y. Chen, N. J. Warter, and W. W. Hwu, "IMPACT: An architectural framework for multiple-instruction-issue processors," in Proceedings of the 18th International Symposium on Computer Architecture, pp. 266--275, May 1991. http://citeseer.ist.psu.edu/chang91impact.html More
@inproceedings{ chang91impact,
author = "P. P. Chang and S. A. Mahlke and W. Y. Chen and N. J. Warter and W. W. Hwu",
title = "{IMPACT}: An Architectural Framework for Multiple-Instruction-Issue Processors",
booktitle = "Proceedings of the 18th International Symposium on Computer Architecture ({ISCA})",
journal = "ACM Computer Architecture News, SIGARCH",
volume = "19",
number = "3",
publisher = "ACM Press",
address = "New York, NY",
pages = "266--275",
year = "1991",
url = "citeseer.ist.psu.edu/chang91impact.html" }
Citations (may not include all citations):1399 Compilers: Principles (context) - Aho, Sethi et al. - 1986
407 Trace scheduling: A technique for global microcode compactio.. (context) - Fisher - 1981
353 Software Pipelining: An Effective Scheduling Technique for V.. (context) - Lam - 1988
176 Some scheduling techniques and an easily schedulable horizon.. (context) - Rau, Glaeser - 1981
173 Bulldog: A Compiler for VLIW Architectures (context) - Ellis - 1986
130 A VLIW Architecture for a Trace Scheduling Compiler (context) - Colwell, Nix et al. - 1987
110 Available Instruction-Level Parallelism for Superscalar and .. - Jouppi, Wall - 1989
107 Achieving High Instruction Cache Performance with an Optimiz.. (context) - Hwu, Chang - 1989
97 The Architecture of Pipelined Computers (context) - Kogge - 1981
85 Code Scheduling and Register Allocation in Large Basic Block.. (context) - Goodman, Hsu - 1988
84 Reducing the Cost of Branches (context) - McFarling, Hennessy - 1986
82 Limits on Multiple Instruction Issue - Smith, Johnson et al. - 1989
66 Boosting Beyond Static Scheduling in a Superscalar Processor - Smith, Lam et al. - 1990
46 A Study of Scalar Compilation Techniques for Pipelined Super.. (context) - Weiss, Smith - 1987
44 Trace Selection for Compiling Large C Application Programs t.. (context) - Chang, Hwu - 1988
30 Uniform Parallelism Exploitation in Ordinary Programs (context) - Nicolau - 1985
22 An Instruction Issuing Approach to Enhancing Performance in .. (context) - Acosta, Kjelstrup et al. - 1986
19 HPS, A New Microarchitecture: Rationale and Introduction (context) - Patt, Hwu et al. - 1985
17 Inline Function Expansion for Compiling Realistic C Programs (context) - Hwu, Chang - 1989
15 HPSm, a High Performance Restricted Data Flow Architecture H.. (context) - Hwu, Patt - 1986
14 Architecture and Compiler Tradeoffs for a Long Instruction W.. (context) - Cohn, Gross et al. - 1989
11 Efficient Instruction Sequencing with Inline Target Insertio.. - Hwu, Chang - 1990
10 Tradeoffs in Instruction Format Design for Horizontal Archit.. (context) - Sohi, Vajapeyam - 1989
9 Trace Scheduling Optimization in a Retargetable Microcode Co.. (context) - Howland, Mueller et al. - 1987
9 MIPS: A VLSI Processor Architecture (context) - Hennessy, Jouppi et al. - 1981
8 Register Allocation & Spilling Via Graph Coloring (context) - Chaitin - 1982
8 Instruction Scheduling Beyond Basic Blocks (context) - Golumbic, Rainish - 1990
6 Control Flow Optimization for Supercomputer Scalar Processin.. (context) - Chang, Hwu - 1989
5 Code Compaction for Parallel Architectures (context) - Anantha, Long - 1990
4 Forward Semantic: A Compiler-Assisted Instruction Fetch Meth.. (context) - Chang, Hwu - 1989
4 Exploiting Parallel Microprocessor Microarchitectures with a.. (context) - Hwu, Chang - 1988
2 Code Optimization Techniques for Multiple-instruction-issue .. (context) - Chang, Mahlke et al.
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