(Enter summary)
Abstract: This paper evaluates the tradeoffs involved in the design of the
software-extended memory system of Alewife, a multiprocessor architecture
that implements coherentsharedmemory through a combination
of hardware and software mechanisms. For each block of
memory, Alewife implements between zero and five coherence directory
pointers in hardwareand allows software to handle requests
when the pointers are exhausted. The software includes a flexible
coherence interface that facilitates protocol... (Update)
Context of citations to this paper: More
.... protocols [52] and interfaces that allow user level programs to build their own customized shared memory cache coherence protocols [10, 33, 42]. Examples of the benefits of carefully chosen primitive interfaces are also common in operating systems research for purposes as...
.... to propose building cache controllers that can execute a variety of caching protocols [6, 21] support multiple communication models [8, 11], or accept guidance from software [12, 17] We are investigating cache designs that will implement a variety of caching protocols,...
Cited by: More
SUDS: Automatic Parallelization for Raw Processors - Frank (2003)
(Correct)
Dynamic Computation Migration in Distributed Shared Memory Systems - Hsieh (1995)
(Correct)
High-Performance All-Software Distributed Shared Memory - Johnson (1995)
(Correct)
Similar documents (at the sentence level):
41.3%: Mechanisms and Interfaces for Software-Extended Coherent Shared.. - Chaiken (1994)
(Correct)
Active bibliography (related documents): More All
0.3: Architectural Support for an Efficient Implementation of a.. - Grahn, Stenström (1995)
(Correct)
0.3: The MIT Alewife Machine: Architecture and Performance - Agarwal, Bianchini, Chaiken, .. (1995)
(Correct)
0.2: Spinning-on-Coherency: A New VSM Optimisation for.. - Nisbet, Ford (1996)
(Correct)
Similar documents based on text: More All
0.2: Integrated Shared-Memory and Message-Passing Communication in.. - Kubiatowicz (1998)
(Correct)
0.2: Multiprocessor Address Tracing and Performance Analysis - Kranz, Chaiken, Agarwal
(Correct)
0.2: Cache Coherence Protocols for Large-Scale Multiprocessors - Chaiken (1990)
(Correct)
Related documents from co-citation: More All
36: Tempest and Typhoon: User-Level Shared Memory
- Reinhardt, Larus et al. - 1994
22: The Stanford FLASH Multiprocessor (context) - Kuskin - 1994
17: The Stanford Dash Multiprocessor (context) - Lenoski, Laudon et al. - 1992
BibTeX entry: (Update)
David Chaiken and Anant Agarwal. Software-Extended Coherent Shared Memory: Performance and Cost. In Proceedings of the 21st Annual International Symposium on Computer Architecture, pages 314--324. IEEE, April 1994. http://citeseer.ist.psu.edu/chaiken94softwareextended.html More
@techreport{ chaiken93softwareextended,
author = "D. Chaiken and A. Agarwal",
title = "{SOFTWARE}-{EXTENDED} {COHERENT} {SHARED} {MEMORY}: {PERFORMANCE} {AND} {COST}",
number = "MIT/LCS/TM-493",
pages = "21",
year = "1993",
url = "citeseer.ist.psu.edu/chaiken94softwareextended.html" }
Citations (may not include all citations):
496
SPLASH: Stanford Parallel Applications for Shared-Memory (context) - Singh, Weber et al. - 1992
478
The Stanford Dash Multiprocessor (context) - Lenoski, Laudon et al. - 1992
443
Improving Direct-Mapped Cache Performance by the Addition of..
- Jouppi - 1990
422
Implementation and Performance of MUNIN
- Carter, Bennett et al. - 1991
408
Multigrid Methods and Applications (context) - Hackbusch - 1985
301
The Midway Distributed Shared Memory System (context) - Bershad, Zekauskas et al. - 1993
195
A New Solution to CoherenceProblems in Multicache Systems (context) - Censier, Feautrier - 1978
191
The MIT Alewife Machine: A LargeScale Distributed-Memory Mul..
- Agarwal - 1991
170
LimitLESS Directories: A Scalable Cache Coherence Scheme
- Chaiken, Kubiatowicz et al. - 1991
157
IVY: A Shared Virtual Memory System for Parallel Computing (context) - Li - 1988
156
An Evaluation of Directory Schemes for Cache Coherence
- Agarwal, Simoni et al. - 1988
113
Directory-Based Cache-Coherence in Large-Scale Multiprocesso.. (context) - Chaiken, Fields et al. - 1990
96
Integrating Message-Passing and Shared-Memory; Early Experie..
- Kranz, Johnson et al. - 1993
94
The DASH Prototype: Logic Overhead and Performance
- Lenoski, Laudon et al. - 1993
92
Cooperative Shared Memory: Software and Hardware for Scalabl..
- Hill, Larus et al. - 1992
87
The Implementation of a Coherent Memory Abstraction on a NUM.. (context) - Cox, Fowler - 1989
66
A HighPerformance Parallel Lisp (context) - Kranz, Halstead et al. - 1989
65
Object Distribution in Orca using Compile-Time and Run-Time ..
- Bal, Kaashoek - 1993
52
An Adaptive Cache Coherence Protocol Optimized for Migratory.. (context) - Stenstrom, Brorsson et al. - 1993
47
Sparcle: An Evolutionary Processor Design for Multiprocessor.. (context) - Agarwal, Kubiatowicz et al. - 1993
43
Software-Controlled Caches in the VMP Multiprocessor (context) - Cheriton, Slavenberg et al. - 1986
37
Concurrent VLSI Architectures (context) - Seitz - 1984
36
An Empirical Evaluation of Two Memory-Efficient Directory Me.. (context) - O'Krafka, Newton - 1990
26
Private Communication (context) - Wood - 1993
14
Dynamic Pointer Allocation for Scalable Cache Coherence Dire..
- Simoni, Horowitz - 1991
11
Massachusetts Institute of Technology (context) - Johnson, Manual et al. - 1991
7
Improving Memory Utilization in Cache Coherence Directories
- Lilja, Yew - 1993
4
Adaptive Cache Coherence for Detecting Migratory Shared Data (context) - Cox, Fowler - 1993
3
A Software Cache Coherence Protocol for Alewife (context) - Piscitello - 1993
2
Massachusetts Institute of Technology (context) - Lim, Parallel et al. - 1993
1
Closing the Window of Vulnerability in Multiphase Memory Tra..
- David, Anant - 1992
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://fermivista.math.jussieu.fr/ftp/ftp.cag.lcs.mit.edu.html): More
Reactive Synchronization Algorithms for Multiprocessors - Lim (1994)
(Correct)
MGS: A Multigrain Shared Memory System - Yeung (1996)
(Correct)
Dribbling Registers: A Mechanism for Reducing Context.. - Vijayaraghavan.. (1992)
(Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC