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Abstract: The Garp compiler and architecture have been developed in parallel, in part to help investigate whether features of the architecture help facilitate rapid, automatic compilation utilizing the Garp's rapidly reconfigurable coprocessor. Previously reported work for compiling to Garp has drawn heavily on techniques from software compilation rather than high-level synthesis. That trend continues in this paper, which describes the extension of those techniques to support pipelined execution of loops ... (Update)
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BibTeX entry: (Update)
Timothy J. Callahan and John Wawrzynek. Adapting Software Pipelining for Reconfigurable Computing. In Pro- ceedings International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES) http://citeseer.ist.psu.edu/callahan00adapting.html More
@inproceedings{ callahan00adapting,
author = "T. Callahan and J. Wawrzynek",
title = "Adapting Software Pipelining for Reconfigurable Computing",
booktitle = "Proceedings of the International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES)",
publisher = "ACM",
address = "San Jose, CA",
year = "2000",
url = "citeseer.ist.psu.edu/callahan00adapting.html" }
Citations (may not include all citations):176 Garp: A MIPS Processor with a Reconfigurable Coprocessor - Hauser, Wawrzynek - 1997
150 Iterative Modulo Scheduling: An Algorithm for Software Pipel.. - Rau - 1994
106 Optimizing Synchronous Systems (context) - Leiserson, Saxe - 1983
47 Code Generation Schema for Modulo Scheduled Loops - Rau, Schlansker et al. - 1992
45 The Garp Architecture and C Compiler (context) - Callahan, Hauser et al. - 2000
40 Hardware-Software Co-Design of Embedded Reconfigurable Archi.. (context) - Li, Callahan et al.
38 The Cydra 5 Departmental Supercomputer: Design Philosophies (context) - Rau, Yen et al. - 1989
27 and Ullman (context) - Aho, Sethi - 1986
26 Instruction-Level Parallelism for Reconfigurable Computing - Callahan, Wawrzynek - 1998
24 ective Compiler Support for Predicated Execution Using the H.. (context) - Mahlke, Lin et al. - 1992
20 ective Scheduling Technique for VLIW Machines (context) - Lam, Pipelining
9 Modulo Scheduling of Loops in Control-Intensive Non-Numeric .. - Lavery, Hwu - 1996
5 cosynthesi to hybrid RISCFPGA architecture (context) - Stone, synthesis et al. - 2000
5 and Implications for Design Automation (context) - DeHon, Wawrzynek
4 IEEE Transactions on Computer-Aided Design of Integrated Cir.. (context) - Weinhardt, Luk
2 Benchmarking Technology for Configurable Computing System (context) - Kumar, Pires et al. - 1998
2 Rapid Module Mapping and Placement for FPGAs (context) - Callahan, Chong et al. - 1998
1 Very High-Level Synthesis of Datapath and Control Structures.. - Moisset, Park et al. - 1999
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