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Abstract: Lowering during standby mode reduces power by decreasing both voltage and current. Analysis of flip-flop structures shows how low the voltage can scale before destroying the state information. Measurements of a 0.13- m, dual--- test chip show that reducing to near the point where state is lost gives the best power savings. We show that "canary" flip-flops provide a mechanism for observing the proximity to failure for the flip-flops. The canary flip-flops enable closed-loop standby voltage... (Update)
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BibTeX entry: (Update)
@misc{ calhoun-standby,
author = "Benton H. Calhoun and Anantha P. Chandrakasan",
title = "Standby Power Reduction Using Dynamic Voltage Scaling and Canary Flip-Flop
Structures",
url = "citeseer.ist.psu.edu/calhoun04standby.html" }
Citations (may not include all citations):64 Design challenges of technology scaling (context) - Borkar - 1999 ACM
24 BSIM: Berkeley shortchannel IGFET model for MOS transistors (context) - Sheu, Scharfetter et al. - 1987
17 Low-power design: Ways to approach the limits (context) - Vittoz - 1994
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1 Ion-implanted complimentary MOS transistors in low-voltage c.. (context) - Swanson, Meindl - 1972
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