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Abstract: Accurate instruction fetch and branch prediction is increasingly important on today's wide-issue architectures. Fetch prediction is the process of determining the next instruction to request from the memory subsystem. Branch prediction is the process of predicting the likely out-come of branch instructions. Several researchers have proposed very effective fetch and branch prediction mechanisms including branch target buffers (BTB) that store the target addresses of taken branches. An... (Update)
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0.4: The Precomputed Branch Architecture - Calder, Grunwald (1999) (Correct)
0.2: Reducing Branch Costs via Branch Alignment - Calder, Grunwald (1994) (Correct)
0.2: Fast Accurate Instruction Fetch and Branch Prediction - Calder, Grunwald (1994) (Correct)
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BibTeX entry: (Update)
B. Calder and D. Grunwald. Next cache line and set prediction. In 22nd Annual International Symposium on Computer Architecture, pages 287--296, June 1995. http://citeseer.ist.psu.edu/calder95next.html More
@inproceedings{ brad95next,
author = "Calder, Brad and Grunwald, Dirk",
title = "{N}ext {C}ache {L}ine and {S}et {P}rediction",
booktitle = "22nd International Symposium on Computer Architecture",
month = "June",
pages = "287-296",
year = "1995",
url = "citeseer.ist.psu.edu/calder95next.html" }
Citations (may not include all citations):386 ATOM: A system for building customized program analysis tool.. (context) - Srivastava, Eustace - 1994
241 A study of branch prediction strategies (context) - Smith - 1981
214 Combining branch predictors - McFarling - 1993
193 Superscalar Microprocessor Design (context) - Johnson - 1991
185 Branch prediction strategies and branch target buffer design (context) - Lee, Smith - 1984
183 Profile guided code positioning (context) - Pettis, Hansen - 1990
119 An enhancedaccess and cycle time model for on-chip caches - andNormanP - 1993
115 Program optimization for instruction caches (context) - McFarling - 1988
110 Improving the accuracy of dynamic branch prediction using br.. (context) - Pan, So et al. - 1992
84 Reducing the cost of branches (context) - McFarling, Hennessy - 1986
71 An area model for on-chip memories and its application (context) - Mulder, Quach et al. - 1991
59 Branch history table prediction of moving target branches du.. (context) - Kaeli, Emma - 1991
34 Branch target buffer design and optimization (context) - Perleberg, Smith - 1993
29 The PowerPC 604 RISC microprocessor (context) - Song, Denman et al. - 1994
28 A comparison of dynamic branch predictors that use two level.. (context) - Yeh, Patt - 1993
24 Alternative implementations of two-level adaptive branch pre.. (context) - Yeh, Patt - 1992
22 accurate instruction fetch andbranch prediction (context) - Calder, Grunwald - 1994
16 Achieving high instruction cache performance with an optimiz.. (context) - Hwu, Chang - 1989
12 Strategies for branch target buffers (context) - Bray, Flynn - 1991
10 Designing the TFP microprocessor (context) - Hsu - 1994
1 Next line prediction apparatus for a pipelined computer syst.. (context) - Steely, Sager - 1994
1 A comprehensive instruction fetch mechanismfor a processor s.. (context) - Yeh, Patt - 1992
The graph only includes citing articles where the year of publication is known.
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Procedure Mapping Using Static Call Graph Estimation - Hashemi, Kaeli, Calder (1997) (Correct)
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