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Abstract: This paper makes the case that pin bandwidth will be a critical consideration for future microprocessors. We show that many of the techniques used to tolerate growing memory latencies do so at the expense of increased bandwidth requirements. Using a decomposition of execution time, we show that for modern processors that employ aggressive memory latency tolerance techniques, wasted cycles due to insufficient bandwidth generally exceed those due to raw memory latencies. Given the importance of... (Update)
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BibTeX entry: (Update)
D. Burger, A. Kagi, and J. R. Goodman. Memory bandwidth limitations of future microprocessors. In Proceedings of the 23rd International Symposium on Computer Architecture, Philadelphia, PA, May 1996. http://citeseer.ist.psu.edu/burger96memory.html More
@inproceedings{ burger96memory,
author = "Doug Burger and James R. Goodman and Alain Kagi",
title = "Memory Bandwidth Limitations of Future Microprocessors",
booktitle = "{ISCA}",
pages = "78-89",
year = "1996",
url = "citeseer.ist.psu.edu/burger96memory.html" }
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41 and Allan Porterfield (context) - Callahan, Kennedy - 1991
30 The Declining Effectiveness of Dynamic Caching for General-P.. - Burger, Kagi et al. - 1995
26 Store Instruction Latencies (context) - Abraham, Sugumar et al. - 1993
17 A Performance Study of Software and Hardware Data Prefetchin.. (context) - Chen, Baer - 1994
13 Creating a Wider Bus Using Caching Techniques - Citron, Rudolph - 1995
3 International Symposium on Shared Memory Multiprocessing (context) - Baskett - 1991
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