(Enter summary)
Abstract: The increasing demand for complex and specialized embedded
hardware must be met by processors which are optimized for
performance, yet are also extremely flexible. In our work, we
explore the tradeoff between flexibility and performance in the
domain of reconfigurable processor design. Specifically, we seek
to identify regularly occurring, computation-heavy patterns in an
application or set of applications. These patterns become
candidates for hard-logic implementation, potentially embedded
in... (Update)
Cited by: More
Exploring the Design Space of LUT-based Transparent.. - Yehia, Clark, Mahlke.. (2005)
(Correct)
Scalable Subgraph Mapping for Acyclic Computation.. - Clark, Hormati, Mahlke.. (2006)
(Correct)
Automated Custom Instruction Generation for.. - Clark, Zhong, Mahlke (2005)
(Correct)
Active bibliography (related documents): More All
0.5: A High-speed DES Implementation for Network Applications - Eberle (1992)
(Correct)
0.5: A VHDL Component Model for Mixed Abstraction Level.. - Hansen, Bringmann..
(Correct)
0.4: Instruction Generation for Hybrid Reconfigurable Systems - Kastner (2001)
(Correct)
Similar documents based on text: More All
0.5: High-Level Data Communication Optimization for.. - Kaplan, Sarrafzadeh..
(Correct)
0.5: Data Communication Estimation and Reduction for - Reconfigurable Systems Adam
(Correct)
0.4: Methodolgies for Predictability Optimization - Srivastava (2002)
(Correct)
Related documents from co-citation: More All
7: Automatic ApplicationSpecific Instruction-Set Extensions under Microarchitectura..
- Atasu, Pozzi et al. - 2003
5: Processor acceleration through automated instruction set customisation
- Clark, Zhong et al. - 2003
5: Code generation using tree pattern matching and dynamic programming (context) - Aho, Ganapathi et al. - 1989
BibTeX entry: (Update)
Philip Brisk, Adam Kaplan, Ryan Kastner, and Majid Sarrafzadeh. Instruction generation and regularity extraction for reconfigurable processors. In Proceedings of CASES 2002. http://citeseer.ist.psu.edu/brisk02instruction.html More
@misc{ brisk02instruction,
author = "P. Brisk and A. Kaplan and R. Kastner and M. Sarrafzadeh",
title = "Instruction generation and regularity extraction for reconfigurable processors",
text = "Philip Brisk, Adam Kaplan, Ryan Kastner, and Majid Sarrafzadeh. Instruction
generation and regularity extraction for reconfigurable processors. In Proceedings
of CASES 2002.",
year = "2002",
url = "citeseer.ist.psu.edu/brisk02instruction.html" }
Citations (may not include all citations):
197
Maximizing Multiprocessor Performance with the SUIF Compiler
- Hall, Anderson et al. - 1996
66
The Generation of Optimal Code for Arithmetic Expressions (context) - Sethi, Ullman - 1970
53
Optimal Code Generation for Expression Trees (context) - Aho, Johnson - 1976
48
Instruction-Set Matching and Selection for DSP and ASIP Code.. (context) - Liem, May et al. - 1994
27
Fast Module Mapping and Placement for Datapaths in FPGAs
- Callahan, Chong et al. - 1998
23
PipeRench: A Reconfigurable Architecture and Compiler
- Goldstein, Schmit et al. - 2000
19
Exploiting Regularity for LowPower Design
- Mehra, Rabaey - 1996
15
Performance Optimization Using Template Mapping for Datapath.. (context) - Corazao, Khalaf et al. - 1996
15
The Block Cipher Rijndael (context) - Daemen, Rijmen - 2000
15
Instruction Set Definition and Instruction Selection for ASI..
- Van Praet, Goossens et al. - 1994
13
On Clustering for Maximal Regularity Extraction (context) - Rao, Kurdahi - 1993
12
A Super-Scheduler for Embedded Reconfigurable Systems
- Memik, Bozorgzadeh et al. - 2001
10
Instruction Generation for Hybrid Reconfigurable Systems
- Kastner, Memik et al. - 2001
7
An Improved Algorithm for Matching Large Graphs (context) - Foggia, Sansone et al. - 2001
4
Totem: Custom Reconfigurable Array Generation
- Compton, Hauck - 2001
4
Matching a Parts Library in a Silicon Compiler (context) - Kahrs - 1986
2
Guidelines for Implementing and Using the NBS Data Encryptio.. (context) - of, NBS - 1981
2
Cross-Level Hierarchical High-Level Synthesis (context) - Bringmann, Rosenstiel - 1998
1
Recursive Construction of Karhunen-Loeve Expansions for Patt.. (context) - Oja, Karhunen - 1980
1
Scheduling Using Behavioral Templates (context) - Tai, Knapp et al. - 1995
1
CathedralHI: Architecture-Driven High-Level Synthesis for Hi.. (context) - Note, Geurts et al. - 1991
The graph only includes citing articles where the year of publication is known.
Documents on the same site (http://www.ece.ucsb.edu/~kastner/publications/publications.html): More
3-D Floorplanning: Simulated Annealing and Greedy.. - Bazargan, Kastner..
(Correct)
On the Sensitivity of Incremental Algorithms for.. - Kastner, Hsieh.. (2002)
(Correct)
Complexity Issues in Gate Duplication - Srivastava, Kastner, Sarrafzadeh (2000)
(Correct)
Online articles have much greater impact More about CiteSeer.IST Add search form to your site Submit documents Feedback
CiteSeer.IST - Copyright Penn State and NEC