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Abstract: Formal synthesis has become an interesting alternative towards post-synthesis verification. Formal synthesis means integrating formal validation within the synthesis process by performing synthesis via rule applications. The practical applicability of formal synthesis very much depends on the efficiency of the underlying rules. This paper gives a case study about the complexity of formal synthesis programs. Experiments with two realistic-sized benchmark circuits were performed using the formal... (Update)
Context of citations to this paper: More
...to the original HOL system, it has been made more efficient by changing the term representation and adding two core functions. See [22] for a detailed description and discussion about this. As we have demonstrated in the paper, the result of our synthesis process is a...
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BibTeX entry: (Update)
C. Blumenrohr et al. On the efficiency of formal synthesis --- experimental results. IEEE Transactions on CAD, 18(1):25--32, 1999. http://citeseer.ist.psu.edu/blumenrohr99efficiency.html More
@misc{ blumenrohr99efficiency,
author = "C. Blumenrohr",
title = "the efficiency of formal synthesis --- experimental results",
text = "C. Blumenrohr et al. On the efficiency of formal synthesis --- experimental
results. IEEE Transactions on CAD, 18(1):25--32, 1999.",
year = "1999",
url = "citeseer.ist.psu.edu/blumenrohr99efficiency.html" }
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3 Applicability of formal synthesis illustrated via scheduling - Blumenrohr, Eisenbiegler et al. - 1996
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1 Transformational design of digital systems based on graph re.. - Huijs - 1996
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