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Abstract: this paper, we examine the relationship between these factors in the context of large-scale, network-based, cache-coherent, shared-memory multiprocessors. Prompted by expected increases in interconnection network bandwidth (particularly with the use of optical networks), we consider whether or not increased bandwidth can be used to reduce the average cost of remote references through an increase in the cache block size. Larger cache blocks often result in reduced miss rates and, given... (Update)
Context of citations to this paper: More
...improvements seen by increasing the line size are progressively smaller for each increase. This is in agreement with the results in [11]. The exception to the above observations is mp3d under software coherence, where increases in line size hurt performance. The reason for this...
...(such as finite sized caches, or network contention) or assume a different architecture. We addressed these concerns in [Bianchini and LeBlanc, 1994], where we studied the relationship between cache block size and application performance as a function of remote access...
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A Preliminary Evaluation of Cache-Miss-Initiated.. - Bianchini, LeBlanc (1994) (Correct)
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BibTeX entry: (Update)
R. Bianchini and T. J. LeBlanc. Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors? In Proceedings of the 1994 International Conference on Parallel Processing, St. Charles, IL, August 1994. Expanded version available as TR 486, Computer Science Department, University of Rochester, January 1994. http://citeseer.ist.psu.edu/bianchini94can.html More
@techreport{ bianchini94can,
author = "Ricardo Bianchini and Thomas J. LeBlanc",
title = "Can High Bandwidth and Latency Justify Large Cache Blocks in Scalable Multiprocessors?",
number = "TR486",
year = "1994",
url = "citeseer.ist.psu.edu/bianchini94can.html" }
Citations (may not include all citations):496 SPLASH: Stanford Parallel Applications for Shared-Memory (context) - Singh, Weber et al. - 1992
357 The Directory-Based Cache Coherence Protocol for the DASH Mu.. (context) - Lenoski, Laudon et al. - 1990
71 Limits on Interconnection Network Performance - Agarwal - 1991
65 Eliminating False Sharing (context) - Eggers, Jeremiassen - 1991
64 Cache Invalidation Patterns in SharedMemory Multiprocessors (context) - Gupta, Weber - 1992
61 The Effect of Sharing on the Cache and Bus Performance of Pa.. (context) - Eggers, Katz - 1989
57 The Detection and Elimination of Useless Misses in Multiproc.. - Dubois, Skeppstedt et al. - 1993
41 Restructuring a Parallel Simulation to Improve Cache Behavio.. - Cheriton, Goosen et al. - 1991
36 Memory Reference Characteristics of Multiprocessor Applicati.. (context) - Agarwal, Gupta - 1988
34 The Performance Impact of Block Sizes and Fetch Strategies (context) - Przybylski - 1990
30 Mint Tutorial and User Manual - Veenstra - 1993
20 Multiprocessor Cache Design Considerations (context) - Lee, Yew et al. - 1987
19 Parallel Block Matrix Factorizations on the Shared-Memory Mu.. (context) - Dackland, Elmroth et al. - 1992
17 Line (Block) Size Choice for CPU Cache Memories (context) - Smith - 1987
5 Problem Decomposition and Communication Tradeoffs in a Share.. (context) - LeBlanc - 1988
2 The Effects of Block Size on the Performance of Coherent Cac.. (context) - Dubnicki - 1993
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MINT: A Front End for Efficient Simulation of Shared-Memory.. - Jack Veenstra (1994) (Correct)
High Performance Synchronization Algorithms for Multiprogrammed.. - Extend Ed (Correct)
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