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Abstract: including synthesis of applicationspecific instruction processors (ASIPs) [43], nor do we explore cosynthesis for control-dominant systems, such as those based on procedural language specifications [22], communicating sequential processes [50], and finite state machine models [6]. All of these are important directions within cosynthesis research, but they do not fit centrally within the DSP-oriented scope of this chapter. Motivation for coarse-grain dataflow specification stems from the... (Update)
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...seen. Where some former tools looked at FPGA s as coprocessors, and thus focused on issues of hardware software co synthesis (e.g. see [21] [22]) today s FPGA have the possibility of being used as complete processing subsystems. This larger scale of device presents problems such...
.... would provide an excellent foundation for research work in automated partitioning and mapping for hardware software co synthesis [ 18]. Each platform to be used in the Logic Foundry requires that implementation specific portals are written for that platform. Once this...
Cited by: More
Goal-Driven Reconfiguration of Polymorphous Architectures - Lohani, Bhattacharyya (2002) (Correct)
Logic Foundry: Rapid Prototyping of FPGA-based DSP Systems - Spivey, Bhattacharyya.. (2003) (Correct)
Logic Foundry: A Rapid Prototyping Tool for FPGA-based.. - Spivey, Bhattacharyya, .. (2002) (Correct)
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3: for Simulink Reference Guide (context) - Generator - 2000
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BibTeX entry: (Update)
S. S. Bhattacharyya, "Hardware/software co-synthesis of DSP systems", In Y. H. Hu, editor, Programmable Digital Signal Processors: Architecture, Programming, and Applications, pages 333-378. Marcel Dekker, 2002. http://citeseer.ist.psu.edu/bhattacharyya01hardwaresoftware.html More
@misc{ bhattacharyya02hardwaresoftware,
author = "S. Bhattacharyya",
title = "Hardware/software co-synthesis of DSP systems",
text = "S. S. Bhattacharyya, Hardware/software co-synthesis of DSP systems, In
Y. H. Hu, editor, Programmable Digital Signal Processors: Architecture,
Programming, and Applications, pages 333-378. Marcel Dekker, 2002.",
year = "2002",
url = "citeseer.ist.psu.edu/bhattacharyya01hardwaresoftware.html" }
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1 Hardware/Software Architectures for Real-Time Caching (context) - Jacob - 1999
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Optimal Parenthesization Of Lexical Orderings For DSP.. - Bhattacharyya, Murthy.. (1995) (Correct)
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