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Abstract: This paper studies value predictor design under table access latency and energy constraints for high-frequency, wide-issue microprocessors. Previous value prediction e#orts make generous assumptions regarding table sizes and access conditions, while ignoring prediction latencies and energy issues. Our work shows that the latency of a high-performance value predictor cannot be completely hidden by the early stages of the instruction pipeline as previously assumed, and causes noticeable... (Update)
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BibTeX entry: (Update)
@misc{ bhargava-value,
author = "Ravi Bhargava and Lizy K. John",
title = "Value Prediction Design for High-Frequency Microprocessors",
url = "citeseer.ist.psu.edu/bhargava02value.html" }
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