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Abstract: In the age of submicron technology a single chip may contain tens or even hundreds of millions transistors. The task of making such enormous systems correct becomes a true challenge for the engineers. Pure simulation can only examine a tiny portion of the functionality of such devices, and can easily miss important errors. Formal verification has a potential of proving correctness of the designs mathematically. There has been significant progress in the past few years in the size and complexity ... (Update)
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BibTeX entry: (Update)
@misc{ berezin-combining,
author = "Sergey Berezin",
title = "Combining Model Checking and Theorem Proving in Hardware Verification",
url = "citeseer.ist.psu.edu/berezin99combining.html" }
Citations (may not include all citations):315 Symbolic Model Checking: An Approach to the State Explosion .. (context) - McMillan - 1993
100 Automatic verification of pipelined microprocessor control - Burch, Dill - 1994
96 Expressing interesting properties of programs in proposition.. (context) - Wolper - 1986
38 and Compositional Verification (context) - Long, Abstraction - 1993
23 Combining symbolic model checking with uninterpreted functio.. - Berezin, Biere et al. - 1998
20 Also appears in Tutorial Notes (context) - Shankar, Owre et al. - 1993
18 Decomposing the proof of correctness of pipelined microproce.. - Hosabettu, Srivas et al.
9 Formal verification of out-of-order execution using incremen.. (context) - Skakkebaek, Jones et al.
7 IEEE Standard for Futurebus+---Logical Protocol Specificatio.. (context) - Society - 1994
6 Symmetry and induction in model checking (context) - Clarke, Jha - 1995
3 Computer Aided Verification (context) - Aided, To - 1998
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