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Abstract: In order to increase performance, circuit designers are beginning to move away from traditional, synchronous designs based on static logic. Recent design examples have shown that significant performance gains are realized when aggressive circuit styles are used. Circuit correctness in these aggressive circuit styles is highly timing dependent, and in industry they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms to explore... (Update)
Context of citations to this paper: More
...certain cases, interleavings can be eliminated by a structural examination of the Petri net. The details of this process are explained in [20]. It does not add significant overhead to the POSet al.gorithm, and in some cases drastically reduces the number of regions explored....
.... when modeling even simple logic functions [30] This increases the size of the reachable state space and makes specification di#cult [2]. This paper uses level ruled Petri nets (LPNs) which are a hybrid of Petri nets and timed automata. They are transition based but...
Cited by: More
Relative Timing Based Verification of Timed Circuits and Systems - Hoshik Kim And (1999) (Correct)
Correctness and Reduction in Timed Circuit Analysis - Mercer (2002) (Correct)
Modular Synthesis of Timed Circuits using Partial Orders on LPNs - Mercer, Myers (2002) (Correct)
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3: Timing assumptions and verification of finite-state concurrent systems (context) - Dill - 1989
3: Some progress in the symbolic verification of timed automata - Bozga, Maler et al. - 1997
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BibTeX entry: (Update)
W. Belluomini. Algorithms for Synthesis and Verification of Timed Circuits and Systems. PhD thesis, University of Utah, 1999. http://citeseer.ist.psu.edu/belluomini99algorithm.html More
@phdthesis{ belluomini99algorithms,
author = "Wendy Belluomini",
title = "Algorithms for Synthesis and Verification of Timed Circuits and Systems",
year = "1999",
url = "citeseer.ist.psu.edu/belluomini99algorithm.html" }
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Documents on the same site (http://www.async.elen.utah.edu/publications.html): More
Verification of Delayed-Reset Domino Circuits Using ATACS - Belluomini, Myers, Hofstee (1999) (Correct)
Covering Conditions and Algorithms for the Synthesis of.. - Beerel, Myers, Meng (1998) (Correct)
Stochastic Cycle Period Analysis in Timed Circuits - Mercer (1999) (Correct)
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