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Abstract: The design of modern embedded systems require automated modeling tools for faster design and for the study of various design trade-o s. These tools put together constitutes an integrated environment, where the designer can write the high level design speci cation and the tools will automatically generate the required hardware and software for the embedded system. Sim-nML is one of these types of speci cation based development system, encircling which several tools have been developed ... (Update)
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0.7: Retargettable Code Generation using Sim-nML - Machine Description In (1998) (Correct)
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BibTeX entry: (Update)
@misc{ basu-high,
author = "Souvik Basu",
title = "High Level Synthesis from Sim-nML Processor",
url = "citeseer.ist.psu.edu/basu99high.html" }
Citations (may not include all citations):217 High Level Synthesis Introduction to Chip and Systems Design (context) - Gajski, Dutt et al. - 1992
79 Automated Synthesis of Data Paths in Digital Systems (context) - Tseng, Siewiorek - 1986
66 ISDL: An Instruction Set Description Language for Retargetab.. - Hadjiyiannis, Hanono et al. - 1997
65 EXPRESSION: A Language for Architecture Exploration through .. - Halambi, Grun et al. - 1999
49 MAHA: A Program for Data Path Synthesis (context) - Parker, Mlinar et al. - 1986
33 LISA - Machine Description Language and Generic Machine Mode.. - Zivojnovic, Pees et al. - 1996
32 Cathedral-III: Architecture Driven High-Level Synthesis for .. (context) - Note, Geurts et al. - 1991
25 High-Level Synthesis of Nonprogrammable Hardware Accelerator.. - Schreiber, Aditya et al. - 2000
24 Design Tools for Intelligent Silicon Compilation (context) - Pangrle, Gajski - 1987
20 The System Architect's Workbench - Thomas, Dirkes et al.
19 Verilog HDL A Guide to Digital Design and Synthesis (context) - Palnitkar - 1996
17 Hardware Synthesis from Term Rewriting Systems - Hoe - 1999
16 Instruction Set Selection for ASIP Design - Gschwind - 1999
15 The MIMOLA Design system : Tools for the Design of Digital P.. (context) - Marwedel - 1984
11 Generation of Hardware Machine Models from Instruction Set D.. - Fauth, Freericks et al. - 1993
11 NEAT: an Object Oriented High Level Synthesis Interface - Heijligers - 1994
11 AMICAL: An Interactive High Level Synthesis Environment (context) - Jerraya, Park et al. - 1993
9 Matching System and Component Behaviour in MIMOLA Synthesis .. - Marwedel - 1990
9 The Olympus Synthesis System for Digital Design (context) - DeMicheli, Ku et al. - 1990
9 Scheduling Between Basic Blocks in the CADDY Synthesis Syste.. - Gutberlet, Muller et al. - 1992
9 High Level Synthesis and Generating FPGAs with the BEDROC sy.. (context) - Leeser, Chapman et al. - 1993
7 The Siemens High Level Synthesis System: CALLAS (context) - Biesenack - 1992
7 Describing Instruction Sets Using nML (Extended Version (context) - Fauth, Praet et al. - 1995
6 Disassembler Using High-Level Processor Models - Jain - 1999
6 PHIDEO: High Level Synthesis for High Throughput Application.. (context) - Meerbergen, Lippens et al. - 1995
5 IMPACT: A High-Level Synthesis System for Low Power Control-.. - Khouri, Lakshminarayana et al. - 1998
4 A Global, Dynamic Register Allocation and Binding for a Data.. (context) - Woo - 1990
4 Retargetable Functional Simulator - Chandra - 1999
3 NESCIO: An Interactive High Level Synthesis Framework - Hilderink - 1994
3 Retargetable Pro ling Tools and their Application in Cache S.. (context) - Rajiv - 1999
2 Retargettable Code Generation using Sim-nML Machine Descript.. (context) - Pogde - 2000
2 An Automatic Assembler Generator for SimnML Description Lang.. (context) - Kumari - 2000
1 Instruction Set Processor Speci cations (ISPS): The Notion a.. (context) - Barbacci - 1981
1 Synthesis of Application Speci c Instruction Sets (context) - Despian, Huang - 1995
1 Automated Transformation of Algorithms into Register-Transfe.. (context) - Zebo, Krzysztof - 1994
1 Regular Array Synthesis Using Alpha (context) - Doran, Oumarou - 1994
1 A Formal Approch to the Scheduling Problem in High Level Syn.. (context) - Hwang, Lee et al. - 1991
1 Application of a Subset of Ada as an Algorithmic Hardware De.. (context) - Girczyc, Bhur et al. - 1985
1 of Fifth Generation Computer Systems (context) - Synthesis, RODIN - 1992
1 Advanced ASIC Chip Synthesis : Using Synopsys Design Compile.. (context) - Bhatnagar - 1999
1 BECOME: Behavior Level Circuit Synthesis Based on Structure .. (context) - Wei - 1988
1 The VLSI Design Automotion Assistant : Prototype System (context) - Kowalski, Thomas - 1983
1 CONES: A System for Automated Synthesis of VLSI and Programm.. (context) - Stroud - 1986
1 C-Based High-Level Synthesis System, Cyber-Design Experience (context) - Wakabayashi
1 Cadence Inc (context) - Manual
1 Specifying Representations of Machine Instructions (context) - Raksey - 1997
1 Synopsys Inc (context) - Manual
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