Luiz Andre Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, Ben Verghese  Home/Search
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Abstract: The microprocessor industry is currently struggling with higher development costs and longer design times that arise from exceedingly complex processors that are pushing the limits of instructionlevel parallelism. Meanwhile, such designs are especially ill suited for important commercial applications, such as on-line transaction processing (OLTP), which suffer from large memory stall times and exhibit little instruction-level parallelism. Given that commercial applications constitute by far the ... (Update)
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BibTeX entry: (Update)
Luiz A. Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk, Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese. Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing. In Proceedings of the 27th Annual International Symposium on Computer Architecture, Vancouver, Canada, June 12--14 2000. http://citeseer.ist.psu.edu/barroso00piranha.html More
@misc{ barroso00piranha,
author = "L. Barroso and K. Gharachorloo and R. McNamara and A. Nowatzyk and S. Qadeer
and B. Sano and S. Smith and R. Stets and B. Verghese",
title = "Piranha: A Scalable Architecture Based on Single-Chip Multiprocessing",
text = "Luiz A. Barroso, Kourosh Gharachorloo, Robert McNamara, Andreas Nowatzyk,
Shaz Qadeer, Barton Sano, Scott Smith, Robert Stets, and Ben Verghese. Piranha:
A Scalable Architecture Based on Single-Chip Multiprocessing. In Proceedings
of the 27th Annual International Symposium on Computer Architecture, Vancouver,
Canada, June 12--14 2000.",
year = "2000",
url = "citeseer.ist.psu.edu/barroso00piranha.html" }
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Performance of Database Workloads on Shared-Memory .. - Ranganathan.. (1998) (Correct)
Memory System Characterization of Commercial Workloads - Barroso, Gharachorloo.. (1998) (Correct)
Impact of Chip-Level Integration on Performance of OLTP.. - Luiz Andr Barroso (2000) (Correct)
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