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Abstract: With increasing chip densities, future microprocessor designs have the opportunity to integrate many of the traditional systemlevel modules onto the same chip as the processor. Some current designs already integrate extremely large on-chip caches, and there are aggressive next-generation designs that attempt to also integrate the memory controller, coherence hardware, and network router all onto a single chip. The tight coupling of these modules will enable efficient memory systems with... (Update)
Context of citations to this paper: More
...databases and web servers. These commercial workloads spend up to one quarter of their total execution time in the operating system [3]. Simulators with high functional fidelity, called full system simulators, can simulate OS code because they precisely model devices (e.g....
.... loads on the memory system, compared to the computation bound applications in our study, but OLTP and DSS have distinct characteristics [16, 19, 2, 4]. DSS workloads would easily fit into the cache sensitive applications in our study. The L1 instruction cache miss rates of the...
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BibTeX entry: (Update)
L. A. Barroso, K. Gharachorloo, A. Nowatzyk, and B. Verghese. Impact of Chip-Level Integration on Performance of OLTP Workloads. In 6th International Symposium on High-Performance Computer Ar- 12 chitecture, pages 3-14, January 2000. http://citeseer.ist.psu.edu/barroso00impact.html More
@inproceedings{ barrosoimpact,
author = "L. Barroso and K. Gharachorloo and A. Nowatzyk and B. Verghese",
title = "Impact of Chip-Level Integration on Performance of {OLTP} Workloads",
pages = "3--14",
url = "citeseer.ist.psu.edu/barroso00impact.html" }
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