Sanjeev Banerjia, Sumedh W. Sathaye, Kishore N. Menezes, Thomas M. Conte  Home/Search
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Abstract: Many contemporary multiple issue processors employ out-of-order scheduling hardware in the processor pipeline. Such scheduling hardware can yield good performance without relying on compile-time scheduling. The hardware can also schedule around unexpected run-time occurrences such as cache misses. As issue widths increase, however, the complexity of such scheduling hardware increases considerably and can have an impact on the cycle time of the processor. This paper presents the design of a ... (Update)
Context of citations to this paper: More
...they called DIF. We proposed a hardware technique that is similar in spirit but different in implementation called miss path scheduling [8]. These are just early studies, and more work needs to be done here. The architecture of an evolutionary processor What does this mean for...
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BibTeX entry: (Update)
S. Banerjia, S. W. Sathaye, K. N. Menezes and T. M. Conte, "MPS: Miss path scheduling for multiple-issue processors," IEEE Transactions on Computers (to appear), 1998. http://citeseer.ist.psu.edu/banerjia98mps.html More
@article{ banerjia98mps,
author = "Sanjeev Banerjia and Sumedh W. Sathaye and Kishore N. Menezes and Thomas M. Conte",
title = "{MPS}: Miss-Path Scheduling for Multiple-Issue Processors",
journal = "IEEE Transactions on Computers",
volume = "47",
number = "12",
pages = "1382-1397",
year = "1998",
url = "citeseer.ist.psu.edu/banerjia98mps.html" }
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