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Abstract: Instruction cache performance is critical to instruction fetch efficiency and overall processor performance. The layout of an executable has a substantial effect on the cache miss rate during execution. This means that the performance of an executable can be improved significantly by applying a codeplacement algorithm that minimizes instruction cache conflicts. Alternatively, the hardware configuration of the instruction cache itself may greatly influence cache performance. For instance,... (Update)
Context of citations to this paper: More
...Second, our victim buffer is non swapping, meaning that hits in the victim buffer are not promoted back to the main cache. Prior work [4] has shown that a nonswapping victim buffer performs as well as or better than a swapping victim cache, since the caches are never tied up...
...(TRG) and (c) a Conflict Miss Graph. All of these models have been successfully applied in procedure placement: CG in [15, 7] TRG in [6, 1] and CMG in [11] Although the CG exploits interaction between procedures that directly call each other, the TRG and the CMG exploit...
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The New C Standard: An Economic and Cultural Commentary - Jones (2002) (Correct)
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BibTeX entry: (Update)
R. I. Bahar, D. Grunwald, and B. Calder. A comparison of software code reordering and victim buffers. In Computer Architecture News. ACM SIGARCH, March 1999. http://citeseer.ist.psu.edu/bahar99comparison.html More
@misc{ bahar99comparison,
author = "R. Bahar and D. Grunwald and B. Calder",
title = "A comparison of software code reordering and victim buffers",
text = "R. I. Bahar, D. Grunwald, and B. Calder. A comparison of software code
reordering and victim buffers. In Computer Architecture News. ACM SIGARCH,
March 1999.",
year = "1999",
url = "citeseer.ist.psu.edu/bahar99comparison.html" }
Citations (may not include all citations):443 Improving direct-mapped cache performance by the addition of.. - Jouppi - 1990
386 Atom: A system for building customized program analysis tool.. (context) - Srivastava, Eustace - 1994
183 Profile guided code positioning (context) - Pettis, Hansen - 1990
177 Evaluating future microprocessors: The simplescalar tool set - Burger, Austin et al. - 1996
107 Achieving high instruction cache performance with an optimiz.. (context) - Hwu, Chang - 1989
103 Predicting conditional branch directions from previous runs .. (context) - Fisher, Freudenberger - 1992
66 Quantifying behavioral differences between C and C++ program.. - Calder, Grunwald et al. - 1994
64 Improving the accuracy of static branch prediction using bra.. (context) - Young, Smith - 1994
63 Cache performance of the spec benchmark suite - Gee, Hill et al. - 1993
60 Predicting program behavior using real or estimated profiles - Wall - 1991
56 Reducing branch costs via branch alignment - Calder, Grunwald - 1994
53 Procedure placement using temporal ordering information - Gloy, Blockwell et al. - 1997
51 Optimizing instruction cache performance for operating syste.. - Torrellas, Xia et al. - 1995
47 Efficient procedure mapping using cache line coloring - Hashemi, Kaeli et al. - 1997
37 Procedure merging with instruction caches - McFarling - 1991
12 Temporal-based procedure reordering for improved instruction.. - Kalamatianos, Kaeli - 1998
1 presented at 30th International Symposium on Microarchitectu.. (context) - Burger, Austin - 1997
1 Wrong-Path Instruction Preefetching (context) - Pierce, Mudge - 1996
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Procedure Mapping Using Static Call Graph Estimation - Hashemi, Kaeli, Calder (1997) (Correct)
Dynamic Hammock Predication for Non-predicated.. - Klauser, Austin.. (1998) (Correct)
Predictive Techniques for Aggressive Load Speculation - Reinman, Calder (1998) (Correct)
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