See this document in CiteSeerX!

Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture (1998)  (Make Corrections)  (43 citations)
David I. August, Daniel A. Connors, Scott A. Mahlke, John W. Sias, Kevin M. Crozier, Ben-Chung Cheng, Patrick R. Eaton, Qudus B. Olaniran, Wen-mei W. Hwu
Proceedings of the 25th annual international symposium on Computer architecture



  Home/Search   Context   Related

Links:   ACM   DBLP

 
View or download:
uiuc.edu/pub/IMPACT/c...isca98epic.ps
uiuc.edu/IMPACT/ftp/c...isca98epic.ps
uiuc.edu/ece412/pape...isca98epic.pdf
Cached:  PS.gz  PS  PDF   Image  Update  Help

From:  uiuc.edu/IMPACT/pap...fconference (more)
From:  uiuc.edu/Impact/people/...bccheng
(Enter author homepages)

Rate this article: (best)
  Comment on this article  
(Enter summary)

Abstract: Explicitly Parallel Instruction Computing (EPIC) architectures require the compiler to express program instruction level parallelism directly to the hardware. EPIC techniques which enable the compiler to represent control speculation, data dependence speculation, and predication have individually been shown to be very effective. However, these techniques have not been studied in combination with each other. This paper presents the IMPACT EPIC Architecture to address the issues involved in... (Update)

Cited by:   More
DTSVLIW: VLIW Performance with Sequential - Code Alberto Ferreira   (Correct)
In Search of a Program Generator to Implement.. - Cohen, Donadio.. (2005)   (Correct)
Deep Jam: Conversion of Coarse-Grain Parallelism to.. - Carribault, Cohen, Jalby (2005)   (Correct)

Active bibliography (related documents):   More   All
0.5:   Latency Tolerant Architectures - Bennett (1998)   (Correct)
0.4:   Compiler Technology for Future Microprocessors - Hwu, Hank, Gallagher, Mahlke, .. (1995)   (Correct)
0.3:   Compiler and Hardware Predicated Dependency Analysis and Scheduling - Carter (2002)   (Correct)

Similar documents based on text:   More   All
1.0:   Incorporating Predicate Information into Branch Predictors - Simon, Calder, Ferrante (2003)   (Correct)
0.5:   Enhancing Loop Buffering of Media and Telecommunications.. - Sias, Hunter, Hwu (2001)   (Correct)
0.5:   Program Decision Logic Optimization Using Predication And.. - Hwu, August, Sias (2001)   (Correct)

Related documents from co-citation:   More   All
16:   Effective compiler support for predicated execution using the hyperblock - Mahlke - 1992
14:   MediaBench: A Tool for Evaluating and Synthesizing Multimedia and Communications.. - Lee - 1997
12:   A Framework for Balancing Control Flow and Predication - August, Hwu et al. - 1997

BibTeX entry:   (Update)

D. I. August, D. A. Connors, S. A. Mahlke, J. W. Sias, K. M. Crozier, B. Cheng, P. R. Eaton, Q. B. Olaniran, and W. W. Hwu, "Integrated Predicated and Speculative Execution in the IMPACT EPIC Architecture," Proceedings of the 25th International Symposium on Computer Architecture, July 1998. http://citeseer.ist.psu.edu/august98integrated.html   More

@inproceedings{ august98integrated,
    author = "David I. August and Daniel A. Connors and Scott A. Mahlke and John W. Sias and Kevin M. Crozier and Ben-Chung Cheng and Patrick R. Eaton and Qudus B. Olaniran and Wen-mei W. Hwu",
    title = "Integrated predicated and speculative execution in the {IMPACT {EPIC}} architecture",
    booktitle = "Proceedings of the 25th annual international symposium on Computer architecture",
    publisher = "IEEE Computer Society Press",
    address = "1109 Spring Street, Suite 300, Silver Spring, MD 20910, USA",
    year = "1998",
    url = "citeseer.ist.psu.edu/august98integrated.html" }
Citations (may not include all citations):
157   Conversion of control dependence to data dependence (context) - Allen, Kennedy et al. - 1983  ACM   DBLP
130   A VLIW architecture for a trace scheduling compiler (context) - Colwell, Nix et al. - 1987  ACM   DBLP
112   Highly concurrent scalar processing (context) - Hsu, Davidson - 1986  ACM   DBLP
102   Dynamic speculation and synchronization of data dependences - Moshovos, Breach et al. - 1997
98   HPL PlayDoh architecture specification: Version (context) - Kathail, Schlansker et al. - 1994
72   Dynamic memory disambiguation using the memory conflict buff.. - Gallagher, Chen et al. - 1994  ACM   DBLP
66   Boosting beyond static scheduling in a superscalar processor - Smith, Lam et al. - 1990  ACM   DBLP
43   A comparison of full and partial predicated execution suppor.. - Mahlke, Hank et al. - 1995
38   Characterizing the impact of predicated execution on branch .. - Mahlke, Hank et al. - 1994  ACM   DBLP
37   The Cydra 5 departmental supercomputer (context) - Rau, Yen et al. - 1989  ACM
32   Sentinel scheduling: A model for compiler-controlled specula.. (context) - Mahlke, Chen et al. - 1993
28   Speculative execution via address prediction and data prefet.. (context) - Gonzalez, Gonzalez - 1997  ACM   DBLP
27   Guarded execution and branch prediction in dynamic ILP proce.. (context) - Pnevmatikatos, Sohi - 1994
19   HP make EPIC disclosure (context) - Gwennap - 1997
16   Superscalar instruction execution in the 21164 Alpha micropr.. (context) - Edmondson, Rubinfeld et al. - 1995
15   Hewlett Packard Laboratories (context) - Park, Schlansker et al. - 1991
15   The effects of predicated execution on branch prediction (context) - Tyson - 1994  ACM   DBLP
8   Speculative execution exception recovery using write-back su.. - Bringmann, Mahlke et al. - 1993  ACM   DBLP
7   CMOS PA-RISC processor for a new family of workstations (context) - Forsyth, Mangelsdorf et al. - 1991
7   Architecture and Instruction Set reference manual (context) - August, Crozier et al. - 1998
7   Architectural support for compile-time speculation - Smith - 1994
3   Memory conflict buffer for achieving memory disambiguation i.. (context) - Kiyohara, Hwu et al. - 1997
2   CPU: Executing instructions in one clock cycle (context) - Crawford - 1990



The graph only includes citing articles where the year of publication is known.


Documents on the same site (http://www.crhc.uiuc.edu/IMPACT/papers/fconference.html):   More
Optimization of Machine Descriptions for Efficient Use - Gyllenhaal, Hwu, Rau (1996)   (Correct)
Comparing Software and Hardware Schemes For Reducing the.. - Hwu, Conte, Chang (1989)   (Correct)
Enhanced Modulo Scheduling for Loops with Conditional.. - Warter, Haab.. (1992)   (Correct)

Online articles have much greater impact   More about CiteSeer.IST   Add search form to your site   Submit documents   Feedback  

CiteSeer.IST - Copyright Penn State and NEC