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Using Real Hardware to Create an Accurate Timing Model for Execution-Time Analysis (2001)  (Make Corrections)  (7 citations)
Pavel Atanassov, Raimund Kirner, Peter Puschner



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Abstract: This paper describes our experience in establishing such a timing model for one of the microcontrollers widely used in embedded systems (Update)

Context of citations to this paper:   More

.... b) Row[ x= Row[ a, y= Row[ b; paramemter rows Row res[ new Row[3] result row Row t1, t2; temporary rows t1=GE.op1(x[2] y[1]) t2=GE.op2(y[1] x[2] res[0] GE.op3(t1, x[0] res[1] GE.op3(t1, x[1] res[2] GE.op4(t2, y[2] return res; where GE.op1...

Cited by:   More
Clustered Calculation of Worst-Case Execution Times - Ermedahl, Stappert, Engblom (2003)   (Correct)
Timing Analysis of Optimised Code - Kirner, Puschner (2002)   (Correct)
A Modular Tool Architecture for Worst-Case Execution Time Analysis - Ermedahl (2003)   (Correct)

Active bibliography (related documents):   More   All
0.8:   The Programming Language wcetC - Kirner (2001)   (Correct)
0.2:   Using Measurements to Derive the Worst-Case Execution Time - Lindgren, Hansson, Thane (2000)   (Correct)
0.1:   A Modular and Retargetable Framework for Tree-based WCET Analysis - Colin, Puaut (2001)   (Correct)

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4:   Bounding pipeline and instruction cache performance (context) - Healy, Arnold et al. - 1999
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BibTeX entry:   (Update)

Pavel Atanassov, Raimund Kirner, and Peter Puschner. Using real hardware to create an accurate timing model for execution-time analysis. In Proceedings of IEEE Workshop on Real-Time Embedded Systems (RTES'01), London, December 3, 2001. http://citeseer.ist.psu.edu/atanassov01using.html   More

@misc{ atanassov01using,
  author = "P. Atanassov and R. Kirner and P. Puschner",
  title = "Using real hardware to create an accurate timing model for execution-time
    analysis",
  text = "Pavel Atanassov, Raimund Kirner, and Peter Puschner. Using real hardware
    to create an accurate timing model for execution-time analysis. In Proceedings
    of IEEE Workshop on Real-Time Embedded Systems (RTES'01), London, December
    3, 2001.",
  year = "2001",
  url = "citeseer.ist.psu.edu/atanassov01using.html" }
Citations (may not include all citations):
49   Cache Modeling for Real-Time Software: Beyond Direct Mapped .. (context) - Li, Malik et al. - 1996
48   Bounding pipeline and instruction cache performance (context) - Healy, Arnold et al. - 1999
31   Worst case execution time analysis for a processor with bran.. (context) - Colin, Puaut - 2000
19   Pipeline Timing Analysis Using a Trace-Driven Simulator - Engblom, Ermedahl - 1999
15   A Review of WorstCase Execution-Time Analysis (context) - Puschner, Burns
12   Making worst case execution time analysis for hard real-time.. - Petters, Frber - 1999
3   Supporting ControlFlow -Dependent Execution Times on WCET Ca.. - Kirner, Puschner
2   Consideration of Optimizing Compilers in the Context of WCET.. - Kirner, Puschner - 2000
1   Whyvqh#v''sh8'pyr# 6pp...h#r8QVTvyh#'...hthv+#SrhyCh.. (context) - Montn, Engblom - 2000
1   8 %&8S#8 %&TS# %# 7v#Tvtyr#8uvfHvp...'p'#...'yyr...#9h#.. (context) - AG - 2000
1   Whyvqh#vth X'...+##8h+r@`rp#v'Uvr6hy'+v+Hr#u'qs'...h .. (context) - Engblom, Ermedahl et al. - 2000
1   Structured Testing of Worst-Case Execution Time Analysis Met.. - Engblom, Ermedahl et al. - 2000
1   D+#...p#v'Tr#Hhhys'...#ur8 %` Ahvy''sTvrr+ %#7v#8HP.. (context) - AG - 1997
1   8 %&8S9r...vo/ooh#vo/oor+# %#7v#Tvtyr#8uvfHvp...'p'#...'y.. (context) - AG - 2000
1   ssvpvr#Ef8hpur H'qryvts'...X8@U6hy'+v (context) - Kirner, Puschner



The graph only includes citing articles where the year of publication is known.


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Simulation and Verification of Embedded Real-time.. - Belarbi, Schwarz (2001)   (Correct)
A Framework for Probabilistic Analysis of.. - Nissanke, Leulseged.. (2001)   (Correct)
An User-Oriented Testing of Real Time Systems - Fouchal, Petitjean, Salva   (Correct)

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