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Abstract: In order to meet the computational needs of the next decade, shared-memory processors must be scalable. Though single shared-bus architectures have been successful in the past, limited bus bandwidth restricts the number of processors that can be effectively put on a single bus machine. One architecture that has been proposed to solve the limited bandwidth problem connects processors using a tree hierarchy of buses. In this paper, we present a tool to study a hierarchical bus based shared-memory ... (Update)
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.... Our architectural evaluations are performed on a cycle by cycle execution driven simulator, a modification of Cerberus [BAD89, AB93] The processor module simulates (at a crude level) the pipeline delays of a RISC processor. All instruction references and all private...
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BibTeX entry: (Update)
Craig Anderson and Jean-Loup Baer. A multi-level hierarchical cache coherence protocol for multiprocessors. In Proc. of 7th Int. Parallel Processing Symoposium, pages 142--148, 1993. http://citeseer.ist.psu.edu/anderson93multilevel.html More
@techreport{ anderson92multilevel,
author = "Anderson and Baer",
title = "A Multi-Level Hierarchical Cache Coherence Protocol for Multiprocessors",
number = "TR 92-10-04",
month = "10",
year = "1992",
url = "citeseer.ist.psu.edu/anderson93multilevel.html" }
Citations (may not include all citations):496 Splash: Stanford parallel applications for shared memory (context) - Sing, Weber et al. - 1992
94 The dash prototype: logic overhead and performance - Lenoski, Laudon et al. - 1992
82 A low overhead coherence solution for multiprocessors with p.. (context) - Papamarcos, Patel - 1984
40 the inclusion properties for multi-level cache hierarchies (context) - Baer - 1988
32 bus architecture for shared memory multiprocessors (context) - Jr, cache - 1987
32 A performance study of memory consistency models - Zucker, Baer - 1992
15 Comparative performance evaluation of cache-coherent numa an.. (context) - Stenstroem, Joe et al. - 1992
12 The cerberus multiprocessor simulator (context) - Brooks, Axelrod et al. - 1989
12 Design of an adaptive cache coherence protocol for large sca.. (context) - Yang, Thangadurai et al. - 1992
7 Gaussian techniques on shared-memory multiprocessors (context) - Darmohray - 1988
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